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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2013-04-15 07:46:11 -04:00
commit 17059f972f
233 changed files with 4064 additions and 5375 deletions
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3
.gitignore vendored
View file

@ -25,10 +25,13 @@
#
/MLO
/SPL
/System.map
/u-boot
/u-boot.hex
/u-boot.imx
/u-boot-with-spl.imx
/u-boot-with-nand-spl.imx
/u-boot.map
/u-boot.srec
/u-boot.ldr

5
MAINTAINERS
View file

@ -663,6 +663,7 @@ Fabio Estevam <fabio.estevam@freescale.com>
mx53smd i.MX53
mx6qsabresd i.MX6Q
mx6qsabreauto i.MX6Q
wandboard i.MX6DL/S
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
@ -1029,10 +1030,6 @@ Vladimir Zapolskiy <vz@mleia.com>
devkit3250 lpc32xx
Zhong Hongbo <bocui107@gmail.com>
SMDK6400 ARM1176 (S3C6400 SoC)
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tetsuyuki Kobayashi <koba@kmckk.co.jp>

40
Makefile
View file

@ -46,12 +46,7 @@ HOSTARCH := $(shell uname -m | \
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\).*/cygwin/')
# Set shell to bash if possible, otherwise fall back to sh
SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
else if [ -x /bin/bash ]; then echo /bin/bash; \
else echo sh; fi; fi)
export HOSTARCH HOSTOS SHELL
export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
@ -273,6 +268,7 @@ LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/block/libblock.o
LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
LIBS-y += drivers/crypto/libcrypto.o
LIBS-y += drivers/dma/libdma.o
LIBS-y += drivers/fpga/libfpga.o
LIBS-y += drivers/gpio/libgpio.o
@ -487,12 +483,19 @@ $(obj)u-boot.dis: $(obj)u-boot
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
-O binary $(obj)spl/u-boot-spl \
$(obj)spl/u-boot-spl-pad.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
$(OBJTREE)/u-boot-with-spl.imx
$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
$(OBJTREE)/u-boot-with-nand-spl.imx
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
@ -782,23 +785,6 @@ $(obj).boards.depend: boards.cfg
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
#########################################################################
## ARM1176 Systems
#########################################################################
smdk6400_noUSB_config \
smdk6400_config : unconfig
@mkdir -p $(obj)include $(obj)board/samsung/smdk6400
@mkdir -p $(obj)nand_spl/board/samsung/smdk6400
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
@if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \
echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
else \
echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
fi
@$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
#########################################################################
#########################################################################
@ -857,6 +843,8 @@ clobber: tidy
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot-with-spl.imx
@rm -f $(obj)u-boot-with-nand-spl.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb

43
README
View file

@ -634,14 +634,6 @@ The following options need to be configured:
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
CONFIG_SYS_NS16550_BROKEN_TEMT
16550 UART set the Transmitter Empty (TEMT) Bit when all output
has finished and the transmitter is totally empty. U-Boot waits
for this bit to be set to initialize the serial console. On some
broken platforms this bit is not set in SPL making U-Boot to
hang while waiting for TEMT. Define this option to avoid it.
- Console Interface:
Depending on board, define exactly one serial port
@ -2839,8 +2831,18 @@ FIT uImage format:
CONFIG_SPL_LDSCRIPT
LDSCRIPT for linking the SPL binary.
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
used by SPL from _start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_MAX_SIZE
Maximum binary size (text, data and rodata) of the SPL binary.
Maximum size of the SPL image (text, data, rodata, and
linker lists sections), BSS excluded.
When defined, the linker checks that the actual size does
not exceed it.
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
@ -2853,7 +2855,11 @@ FIT uImage format:
Link address for the BSS within the SPL binary.
CONFIG_SPL_BSS_MAX_SIZE
Maximum binary size of the BSS section of the SPL binary.
Maximum size in memory allocated to the SPL BSS.
When defined, the linker checks that the actual memory used
by SPL from __bss_start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
@ -2972,8 +2978,11 @@ FIT uImage format:
Support for lib/libgeneric.o in SPL binary
CONFIG_SPL_PAD_TO
Linker address to which the SPL should be padded before
appending the SPL payload.
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
@ -3846,9 +3855,13 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
- CONFIG_SYS_NDFC_16
Defined to tell the NDFC that the NAND chip is using a
16 bit bus.
- CONFIG_SYS_NAND_BUSWIDTH_16BIT
Defined to tell the NAND controller that the NAND chip is using
a 16 bit bus.
Not all NAND drivers use this symbol.
Example of drivers that use it:
- drivers/mtd/nand/ndfc.c
- drivers/mtd/nand/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined

2
arch/arm/config.mk
View file

@ -87,9 +87,7 @@ endif
endif
# needed for relocation
ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
endif
#
# FIXME: binutils versions < 2.22 have a bug in the assembler where

7
arch/arm/cpu/arm1136/config.mk
View file

@ -31,6 +31,13 @@ PLATFORM_CPPFLAGS += -march=armv5
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/SPL
endif
else
ALL-y += $(obj)u-boot.imx
endif
endif

8
arch/arm/cpu/arm1136/omap24xx/timer.c
View file

@ -31,13 +31,16 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/omap2420.h>
#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \
/ (TIMER_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@ -99,7 +102,8 @@ ulong get_timer_masked (void)
gd->arch.tbl += (now - gd->arch.lastinc);
} else {
/* we have rollover of incrementer */
gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ))
- gd->arch.lastinc) + now;
}
gd->arch.lastinc = now;
return gd->arch.tbl;

31
arch/arm/cpu/arm1136/start.S
View file

@ -88,7 +88,11 @@ _end_vect:
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -100,9 +104,9 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.global _image_copy_end_ofs
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
@ -170,29 +174,24 @@ next:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -201,7 +200,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -235,8 +233,6 @@ fixnext:
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
bx lr
#endif
relocate_done:
@ -392,8 +388,9 @@ cpu_init_crit:
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm

2
arch/arm/cpu/arm1136/u-boot-spl.lds
View file

@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
arch/arm/cpu/arm1136/start.o (.text)
arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} >.sram

14
arch/arm/cpu/arm1176/bcm2835/timer.c
View file

@ -23,7 +23,7 @@ int timer_init(void)
return 0;
}
ulong get_timer(ulong base)
ulong get_timer_us(ulong base)
{
struct bcm2835_timer_regs *regs =
(struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
@ -31,6 +31,14 @@ ulong get_timer(ulong base)
return readl(&regs->clo) - base;
}
ulong get_timer(ulong base)
{
ulong us = get_timer_us(0);
us /= (1000000 / CONFIG_SYS_HZ);
us -= base;
return us;
}
unsigned long long get_ticks(void)
{
return get_timer(0);
@ -46,10 +54,10 @@ void __udelay(unsigned long usec)
ulong endtime;
signed long diff;
endtime = get_timer(0) + usec;
endtime = get_timer_us(0) + usec;
do {
ulong now = get_timer(0);
ulong now = get_timer_us(0);
diff = endtime - now;
} while (diff >= 0);
}

34
arch/arm/cpu/arm1176/s3c64xx/config.mk
View file

@ -1,34 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v6.
PLATFORM_CPPFLAGS += -march=armv5t
# =========================================================================
#
# Supply options according to compiler version
#
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

135
arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
View file

@ -1,135 +0,0 @@
/*
* Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
*
* Copyright (C) 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/s3c6400.h>
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
/* DMC1 base address 0x7e001000 */
ldr r0, =ELFIN_DMC1_BASE
ldr r1, =0x4
str r1, [r0, #INDEX_DMC_MEMC_CMD]
ldr r1, =DMC_DDR_REFRESH_PRD
str r1, [r0, #INDEX_DMC_REFRESH_PRD]
ldr r1, =DMC_DDR_CAS_LATENCY
str r1, [r0, #INDEX_DMC_CAS_LATENCY]
ldr r1, =DMC_DDR_t_DQSS
str r1, [r0, #INDEX_DMC_T_DQSS]
ldr r1, =DMC_DDR_t_MRD
str r1, [r0, #INDEX_DMC_T_MRD]
ldr r1, =DMC_DDR_t_RAS
str r1, [r0, #INDEX_DMC_T_RAS]
ldr r1, =DMC_DDR_t_RC
str r1, [r0, #INDEX_DMC_T_RC]
ldr r1, =DMC_DDR_t_RCD
ldr r2, =DMC_DDR_schedule_RCD
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RCD]
ldr r1, =DMC_DDR_t_RFC
ldr r2, =DMC_DDR_schedule_RFC
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RFC]
ldr r1, =DMC_DDR_t_RP
ldr r2, =DMC_DDR_schedule_RP
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RP]
ldr r1, =DMC_DDR_t_RRD
str r1, [r0, #INDEX_DMC_T_RRD]
ldr r1, =DMC_DDR_t_WR
str r1, [r0, #INDEX_DMC_T_WR]
ldr r1, =DMC_DDR_t_WTR
str r1, [r0, #INDEX_DMC_T_WTR]
ldr r1, =DMC_DDR_t_XP
str r1, [r0, #INDEX_DMC_T_XP]
ldr r1, =DMC_DDR_t_XSR
str r1, [r0, #INDEX_DMC_T_XSR]
ldr r1, =DMC_DDR_t_ESR
str r1, [r0, #INDEX_DMC_T_ESR]
ldr r1, =DMC1_MEM_CFG
str r1, [r0, #INDEX_DMC_MEMORY_CFG]
ldr r1, =DMC1_MEM_CFG2
str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
ldr r1, =DMC1_CHIP0_CFG
str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
ldr r1, =DMC_DDR_32_CFG
str r1, [r0, #INDEX_DMC_USER_CONFIG]
/* DMC0 DDR Chip 0 configuration direct command reg */
ldr r1, =DMC_NOP0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
/* Precharge All */
ldr r1, =DMC_PA0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
/* Auto Refresh 2 time */
ldr r1, =DMC_AR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
/* MRS */
ldr r1, =DMC_mDDR_EMR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
/* Mode Reg */
ldr r1, =DMC_mDDR_MR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
/* Enable DMC1 */
mov r1, #0x0
str r1, [r0, #INDEX_DMC_MEMC_CMD]
check_dmc1_ready:
ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
bne check_dmc1_ready
nop
mov pc, lr
.ltorg

26
arch/arm/cpu/arm1176/s3c64xx/init.c
View file

@ -1,26 +0,0 @@
/*
* (C) Copyright 2012 Ashok Kumar Reddy Kourla
* ashokkourla2000@gmail.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include<common.h>
int arch_cpu_init(void)
{
icache_enable();
return 0;
}

34
arch/arm/cpu/arm1176/s3c64xx/reset.S
View file

@ -1,34 +0,0 @@
/*
* Copyright (c) 2009 Samsung Electronics.
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/arch/s3c6400.h>
.globl reset_cpu
reset_cpu:
ldr r1, =ELFIN_CLOCK_POWER_BASE
ldr r2, [r1, #SYS_ID_OFFSET]
ldr r3, =0xffff
and r2, r3, r2, lsr #12
str r2, [r1, #SW_RST_OFFSET]
_loop_forever:
b _loop_forever

145
arch/arm/cpu/arm1176/s3c64xx/speed.c
View file

@ -1,145 +0,0 @@
/*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This code should work for both the S3C2400 and the S3C2410
* as they seem to have the same PLL and clock machinery inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/
#include <common.h>
#include <asm/arch/s3c6400.h>
#define APLL 0
#define MPLL 1
#define EPLL 2
/* ------------------------------------------------------------------------- */
/*
* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
static ulong get_PLLCLK(int pllreg)
{
ulong r, m, p, s;
switch (pllreg) {
case APLL:
r = APLL_CON_REG;
break;
case MPLL:
r = MPLL_CON_REG;
break;
case EPLL:
r = EPLL_CON0_REG;
break;
default:
hang();
}
m = (r >> 16) & 0x3ff;
p = (r >> 8) & 0x3f;
s = r & 0x7;
return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
}
/* return ARMCORE frequency */
ulong get_ARMCLK(void)
{
ulong div;
div = CLK_DIV0_REG;
return get_PLLCLK(APLL) / ((div & 0x7) + 1);
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
return get_PLLCLK(APLL);
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
ulong fclk;
uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
/*
* Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
* s3c6400 and is always 0, and it is indeed running in ASYNC mode
*/
if (OTHERS_REG & 0x80)
fclk = get_FCLK(); /* SYNC Mode */
else
fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
return fclk / (hclk_div * hclkx2_div);
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
ulong fclk;
uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
if (OTHERS_REG & 0x80)
fclk = get_FCLK(); /* SYNC Mode */
else
fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
return fclk / (hclkx2_div * pre_div);
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
return get_PLLCLK(EPLL);
}
int print_cpuinfo(void)
{
printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
get_FCLK() / 1000000, get_HCLK() / 1000000,
get_PCLK() / 1000000);
if (OTHERS_REG & 0x80)
printf("(SYNC Mode) \n");
else
printf("(ASYNC Mode) \n");
return 0;
}

160
arch/arm/cpu/arm1176/s3c64xx/timer.c
View file

@ -1,160 +0,0 @@
/*
* (C) Copyright 2003
* Texas Instruments <www.ti.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002-2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2004
* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/arch/s3c6400.h>
#include <div64.h>
static ulong timer_load_val;
#define PRESCALER 167
static s3c64xx_timers *s3c64xx_get_base_timers(void)
{
return (s3c64xx_timers *)ELFIN_TIMER_BASE;
}
/* macro to read the 16 bit timer */
static inline ulong read_timer(void)
{
s3c64xx_timers *const timers = s3c64xx_get_base_timers();
return timers->TCNTO4;
}
/* Internal tick units */
/* Last decremneter snapshot */
static unsigned long lastdec;
/* Monotonic incrementing timer */
static unsigned long long timestamp;
int timer_init(void)
{
s3c64xx_timers *const timers = s3c64xx_get_base_timers();
/* use PWM Timer 4 because it has no output */
/*
* We use the following scheme for the timer:
* Prescaler is hard fixed at 167, divider at 1/4.
* This gives at PCLK frequency 66MHz approx. 10us ticks
* The timer is set to wrap after 100s, at 66MHz this obviously
* happens after 10,000,000 ticks. A long variable can thus
* keep values up to 40,000s, i.e., 11 hours. This should be
* enough for most uses:-) Possible optimizations: select a
* binary-friendly frequency, e.g., 1ms / 128. Also calculate
* the prescaler automatically for other PCLK frequencies.
*/
timers->TCFG0 = PRESCALER << 8;
if (timer_load_val == 0) {
timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
}
/* load value for 10 ms timeout */
lastdec = timers->TCNTB4 = timer_load_val;
/* auto load, manual update of Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
TCON_4_UPDATE;
/* auto load, start Timer 4 */
timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
timestamp = 0;
return 0;
}
/*
* timer without interrupts
*/
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
ulong now = read_timer();
if (lastdec >= now) {
/* normal mode */
timestamp += lastdec - now;
} else {
/* we have an overflow ... */
timestamp += lastdec + timer_load_val - now;
}
lastdec = now;
return timestamp;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
/* We overrun in 100s */
return (ulong)(timer_load_val / 100);
}
ulong get_timer_masked(void)
{
unsigned long long res = get_ticks();
do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
return res;
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = (usec + 9) / 10;
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp)/* loop till event */
/*NOP*/;
}

131
arch/arm/cpu/arm1176/start.S
View file

@ -33,11 +33,8 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#endif
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
@ -51,7 +48,7 @@
.globl _start
_start: b reset
#ifndef CONFIG_NAND_SPL
#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@ -98,15 +95,11 @@ _end_vect:
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
/*
* Below variable is very important because we use MMU in U-Boot.
* Without it, we cannot run code correctly before MMU is ON.
* by scsuh.
*/
_TEXT_PHY_BASE:
.word CONFIG_SYS_PHY_UBOOT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -119,6 +112,10 @@ _TEXT_PHY_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -164,7 +161,7 @@ cpu_init_crit:
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
#ifndef CONFIG_NAND_SPL
#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
@ -229,29 +226,24 @@ skip_tcmdisable:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -260,7 +252,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -296,44 +287,6 @@ fixnext:
blo fixloop
#endif
#ifdef CONFIG_ENABLE_MMU
enable_mmu:
/* enable domain access */
ldr r5, =0x0000ffff
mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
/* Set the TTB register */
ldr r0, _mmu_table_base
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2, =0xfff00000
bic r0, r0, r2
orr r1, r0, r1
mcr p15, 0, r1, c2, c0, 0
/* Enable the MMU */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1 /* Set CR_M to enable MMU */
/* Prepare to enable the MMU */
adr r1, skip_hw_init
and r1, r1, #0x3fc
ldr r2, _TEXT_BASE
ldr r3, =0xfff00000
and r2, r2, r3
orr r2, r2, r1
b mmu_enable
.align 5
/* Run in a single cache-line */
mmu_enable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
skip_hw_init:
#endif
relocate_done:
bx lr
@ -345,52 +298,12 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
#ifdef CONFIG_ENABLE_MMU
_mmu_table_base:
.word mmu_table
#endif
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
#ifndef CONFIG_NAND_SPL
/*
* we assume that cache operation is done before. (eg. cleanup_before_linux())
* actually, we don't need to do anything about cache if not use d-cache in
* U-Boot. So, in this function we clean only MMU. by scsuh
*
* void theLastJump(void *kernel, int arch_num, uint boot_params);
*/
#ifdef CONFIG_ENABLE_MMU
.globl theLastJump
theLastJump:
mov r9, r0
ldr r3, =0xfff00000
ldr r4, _TEXT_PHY_BASE
adr r5, phy_last_jump
bic r5, r5, r3
orr r5, r5, r4
mov pc, r5
phy_last_jump:
/*
* disable MMU stuff
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov r0, #0
mov pc, r9
#endif
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
@ -480,9 +393,11 @@ phy_last_jump:
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
mrs r0, spsr
mrs lr, spsr
/* save spsr in position 1 of saved stack */
str lr, [r0, #4]
/* restore lr */
ldr lr, [r0]
/* restore r0 */
ldr r0, [r13]
/* pop stack entry */
@ -533,4 +448,4 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_NAND_SPL */
#endif /* CONFIG_SPL_BUILD */

26
arch/arm/cpu/arm720t/start.S
View file

@ -85,7 +85,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */
.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
@ -101,6 +101,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -152,29 +156,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -183,7 +182,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

13
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
View file

@ -31,18 +31,18 @@ SECTIONS
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm920t/start.o (.text)
arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
*(.text)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
.rodata : { *(.rodata*) }
. = ALIGN(4);
.data : { *(.data) }
.data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got) }
@ -55,8 +55,11 @@ SECTIONS
}
. = ALIGN(4);
__image_copy_end = .;
__bss_start = .;
.bss : { *(.bss) }
.bss : { *(.bss*) }
__bss_end = .;
_end = .;

28
arch/arm/cpu/arm920t/start.S
View file

@ -73,7 +73,11 @@ _fiq: .word fiq
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -85,6 +89,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -187,29 +195,24 @@ copyex:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -218,7 +221,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

28
arch/arm/cpu/arm925t/start.S
View file

@ -79,7 +79,11 @@ _fiq: .word fiq
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -91,6 +95,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -177,29 +185,24 @@ poll1:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -208,7 +211,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

10
arch/arm/cpu/arm926ejs/config.mk
View file

@ -33,7 +33,11 @@ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-mali
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
ifdef CONFIG_SPL
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/SPL
endif
else
ALL-y += $(obj)u-boot.imx
endif
endif

18
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View file

@ -46,17 +46,17 @@ static uint32_t dram_vals[] = {
0x00000000, 0x00000000, 0x00010101, 0x01010101,
0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
0x00000100, 0x00000100, 0x00000000, 0x00000002,
0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
0x00000003, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000612, 0x01000F02,
0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
0x07000300, 0x07000300, 0x07000300, 0x00000006,
0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
0x07000300, 0x07400300, 0x07400300, 0x00000005,
0x00000000, 0x00000000, 0x01000000, 0x01020408,
0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
@ -77,14 +77,14 @@ static uint32_t dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00010000, 0x00020304,
0x00000004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00010000, 0x00030404,
0x00000003, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x01010000,
0x01000000, 0x03030000, 0x00010303, 0x01020202,
0x00000000, 0x02040303, 0x21002103, 0x00061200,
0x06120612, 0x04320432, 0x04320432, 0x00040004,
0x06120612, 0x04420442, 0x04420442, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
0x00000000, 0xffffffff
/*
* i.MX23 DDR at 133MHz

4
arch/arm/cpu/arm926ejs/mxs/start.S
View file

@ -119,7 +119,11 @@ fiq:
.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_SPL_TEXT_BASE
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.

6
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
View file

@ -37,8 +37,8 @@ SECTIONS
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm926ejs/mxs/start.o (.text)
*(.text)
arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
*(.text*)
}
. = ALIGN(4);
@ -46,7 +46,7 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
*(.data*)
}
. = ALIGN(4);

15
arch/arm/cpu/arm926ejs/omap/timer.c
View file

@ -36,11 +36,14 @@
*/
#include <common.h>
#include <asm/io.h>
#define TIMER_LOAD_VAL 0xffffffff
#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \
/ (TIMER_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@ -114,7 +117,8 @@ ulong get_timer_masked (void)
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and cause problems.
*/
timestamp += lastdec + TIMER_LOAD_VAL - now;
timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
CONFIG_SYS_HZ)) - now;
}
lastdec = now;
@ -160,8 +164,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CONFIG_SYS_HZ;
return tbclk;
return CONFIG_SYS_HZ;
}

6
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View file

@ -37,8 +37,8 @@ SECTIONS
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm926ejs/spear/start.o (.text)
*(.text)
arch/arm/cpu/arm926ejs/spear/start.o (.text*)
*(.text*)
}
. = ALIGN(4);
@ -46,7 +46,7 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
*(.data*)
}
. = ALIGN(4);

40
arch/arm/cpu/arm926ejs/start.S
View file

@ -120,15 +120,11 @@ _fiq:
.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
.word CONFIG_SYS_TEXT_BASE
#else
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
#endif
/*
* These are defined in the board-specific linker script.
@ -140,6 +136,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -148,12 +148,6 @@ _bss_end_ofs:
_end_ofs:
.word _end - _start
#ifdef CONFIG_NAND_U_BOOT
.globl _end
_end:
.word __bss_end
#endif
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
@ -196,32 +190,25 @@ reset:
/*------------------------------------------------------------------------------*/
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
moveq r9, #0 /* no relocation. offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -230,7 +217,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -270,6 +256,8 @@ relocate_done:
bx lr
#ifndef CONFIG_SPL_BUILD
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:

28
arch/arm/cpu/arm946es/start.S
View file

@ -89,7 +89,11 @@ _vectors_end:
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -101,6 +105,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -152,29 +160,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -183,7 +186,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

30
arch/arm/cpu/arm_intcm/start.S
View file

@ -85,7 +85,11 @@ _fiq:
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -97,6 +101,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -148,29 +156,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -179,7 +182,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

5
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
View file

@ -195,6 +195,11 @@ static void enable_per_clocks(void)
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
;
/* MMC1 */
writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
;
/* i2c0 */
writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)

2
arch/arm/cpu/armv7/am33xx/elm.c
View file

@ -33,7 +33,7 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/cpu.h>
#include <asm/arch/omap_gpmc.h>
#include <asm/omap_gpmc.h>
#include <asm/arch/elm.h>
#define ELM_DEFAULT_POLY (0)

6
arch/arm/cpu/armv7/config.mk
View file

@ -40,5 +40,11 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/SPL
endif
else
ALL-y += $(obj)u-boot.imx
endif
endif

167
arch/arm/cpu/armv7/exynos/clock.c
View file

@ -27,6 +27,49 @@
#include <asm/arch/clk.h>
#include <asm/arch/periph.h>
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
/* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
{12, 12, -1},
{0, 0, 8},
{4, 16, 24},
{8, 0, 8},
{12, 16, 24},
{-1, -1, -1},
{16, 0, 8},
{20, 16, 24},
{24, 0, 8},
{0, 0, 4},
{4, 12, 16},
{-1, -1, -1},
{-1, -1, -1},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
};
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
{ 192000000, 0, 48, 3, 1, 0 },
@ -201,6 +244,107 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
static unsigned long exynos5_get_periph_rate(int peripheral)
{
struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
unsigned long sclk, sub_clk;
unsigned int src, div, sub_div;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
case PERIPH_ID_PWM3:
case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric3);
break;
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
sclk = exynos5_get_pll_clk(MPLL);
sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
& 0x7) + 1;
div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
& 0x7) + 1;
return (sclk / sub_div) / div;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
src = (src >> bit_info->src_bit) & 0xf;
switch (src) {
case EXYNOS_SRC_MPLL:
sclk = exynos5_get_pll_clk(MPLL);
break;
case EXYNOS_SRC_EPLL:
sclk = exynos5_get_pll_clk(EPLL);
break;
case EXYNOS_SRC_VPLL:
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
return 0;
}
/* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
/* Pre-ratio clock division for SDMMC0 and 2 */
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
}
return sub_clk;
}
unsigned long clock_get_periph_rate(int peripheral)
{
if (cpu_is_exynos5())
return exynos5_get_periph_rate(peripheral);
else
return 0;
}
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@ -324,27 +468,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
/* exynos5: return pwm clock frequency */
static unsigned long exynos5_get_pwm_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long pclk, sclk;
unsigned int ratio;
/*
* CLK_DIV_PERIC3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peric3);
ratio = ratio & 0xf;
sclk = get_pll_clk(MPLL);
pclk = sclk / (ratio + 1);
return pclk;
}
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@ -1210,7 +1333,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
return exynos5_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
else {
if (proid_is_exynos4412())
return exynos4x12_get_pwm_clk();

36
arch/arm/cpu/armv7/exynos/soc.c
View file

@ -23,6 +23,14 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
enum l2_cache_params {
CACHE_TAG_RAM_SETUP = (1 << 9),
CACHE_DATA_RAM_SETUP = (1 << 5),
CACHE_TAG_RAM_LATENCY = (2 << 6),
CACHE_DATA_RAM_LATENCY = (2 << 0)
};
void reset_cpu(ulong addr)
{
@ -36,3 +44,31 @@ void enable_caches(void)
dcache_enable();
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Set L2 cache parameters
*/
static void exynos5_set_l2cache_params(void)
{
unsigned int val = 0;
asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
}
/*
* Sets L2 cache related parameters before enabling data cache
*/
void v7_outer_cache_enable(void)
{
if (cpu_is_exynos5())
exynos5_set_l2cache_params();
}
#endif

8
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View file

@ -309,8 +309,7 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02888945
orr r1, r1, #(1 << 16)
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
@ -321,10 +320,7 @@ setup_pll_func:
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
orr r1, r1, #(2 << 10)
orr r1, r1, #(0 << 16)
orr r1, r1, #(1 << 19)
ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154

12
arch/arm/cpu/armv7/mx6/soc.c
View file

@ -61,6 +61,18 @@ u32 get_cpu_rev(void)
return (type << 12) | (reg + 0x10);
}
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
u32 cpurev = get_cpu_rev();
u32 type = ((cpurev >> 12) & 0xff);
if (type == MXC_CPU_MX6SOLO)
cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
return cpurev;
}
#endif
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;

4
arch/arm/cpu/armv7/omap-common/clocks-common.c
View file

@ -612,7 +612,7 @@ void freq_update_core(void)
/*
* Putting EMIF in HW_AUTO is seen to be causing issues with
* EMIF clocks and the master DLL. Put EMIF in SW_WKUP
* EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
* in OMAP5430 ES1.0 silicon
*/
if (omap_rev != OMAP5430_ES1_0) {
@ -659,7 +659,7 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);

29
arch/arm/cpu/armv7/omap-common/emif-common.c
View file

@ -655,20 +655,27 @@ static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
return phy;
}
static u32 get_emif_mem_size(struct emif_device_details *devices)
static u32 get_emif_mem_size(u32 base)
{
u32 size_mbytes = 0, temp;
struct emif_device_details dev_details;
struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
u32 emif_nr = emif_num(base);
if (!devices)
return 0;
emif_reset_phy(base);
dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
&cs0_dev_details);
dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
&cs1_dev_details);
emif_reset_phy(base);
if (devices->cs0_device_details) {
temp = devices->cs0_device_details->density;
if (dev_details.cs0_device_details) {
temp = dev_details.cs0_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
if (devices->cs1_device_details) {
temp = devices->cs1_device_details->density;
if (dev_details.cs1_device_details) {
temp = dev_details.cs1_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
/* convert to bytes */
@ -1040,13 +1047,9 @@ static void do_sdram_init(u32 base)
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
!dev_details.cs1_device_details) {
emif_sizes[emif_nr - 1] = 0;
return;
}
if (!in_sdram)
emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
/*
* Get device timings:
* - Default timings specified by JESD209-2 if
@ -1108,8 +1111,8 @@ void dmm_init(u32 base)
mapped_size = 0;
section_cnt = 3;
sys_addr = CONFIG_SYS_SDRAM_BASE;
emif1_size = emif_sizes[0];
emif2_size = emif_sizes[1];
emif1_size = get_emif_mem_size(EMIF1_BASE);
emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
if (!emif1_size && !emif2_size)

10
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
View file

@ -60,10 +60,14 @@ ENTRY(save_boot_params)
ldr r3, =boot_params
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #BOOT_DEVICE_XIP
/*
* boot mode is only valid for device that can be raw or FAT booted.
* in other cases it may be fatal to look. While platforms differ
* in the values used for each MMC slot, they are contiguous.
*/
cmp r2, #MMC_BOOT_DEVICES_START
blt 2f
cmp r2, #BOOT_DEVICE_MMC2
cmp r2, #MMC_BOOT_DEVICES_END
bgt 2f
/* Store the boot mode (raw/FAT) in omap_bootmode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr

2
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
View file

@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
arch/arm/cpu/armv7/start.o (.text)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram

31
arch/arm/cpu/armv7/omap3/board.c
View file

@ -328,14 +328,25 @@ void abort(void)
*****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
if (argc < 2 || argc > 3)
goto usage;
if (strncmp(argv[1], "hw", 2) == 0)
omap_nand_switch_ecc(1);
else if (strncmp(argv[1], "sw", 2) == 0)
omap_nand_switch_ecc(0);
else
if (strncmp(argv[1], "hw", 2) == 0) {
if (argc == 2) {
omap_nand_switch_ecc(1, 1);
} else {
if (strncmp(argv[2], "hamming", 7) == 0)
omap_nand_switch_ecc(1, 1);
else if (strncmp(argv[2], "bch8", 4) == 0)
omap_nand_switch_ecc(1, 8);
else
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
omap_nand_switch_ecc(0, 0);
} else {
goto usage;
}
return 0;
@ -345,9 +356,13 @@ usage:
}
U_BOOT_CMD(
nandecc, 2, 1, do_switch_ecc,
nandecc, 3, 1, do_switch_ecc,
"switch OMAP3 NAND ECC calculation algorithm",
"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
"hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
" 8-bit BCH\n"
" ecc calculation (second parameter may"
" be omitted).\n"
"nandecc sw - Switch to NAND software ecc algorithm."
);
#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

4
arch/arm/cpu/armv7/omap3/sys_info.c
View file

@ -299,9 +299,9 @@ int print_cpuinfo (void)
}
if ((get_cpu_rev() >= CPU_3XX_ES31) &&
(get_sku_id() == SKUID_CLK_720MHZ))
max_clk = "720 mHz";
max_clk = "720 MHz";
else
max_clk = "600 mHz";
max_clk = "600 MHz";
break;
case CPU_AM35XX:

1
arch/arm/cpu/armv7/omap4/emif.c
View file

@ -33,7 +33,6 @@
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS

8
arch/arm/cpu/armv7/omap4/hw_data.c
View file

@ -216,14 +216,14 @@ struct dplls omap4460_dplls = {
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 10 mV represented in uV */
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 10 mV represented in uV */
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
@ -271,11 +271,11 @@ struct vcores_data omap4460_volts = {
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &tps62361,
.core.pmic = &twl6030,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &tps62361,
.mm.pmic = &twl6030,
};
/*

1
arch/arm/cpu/armv7/omap5/emif.c
View file

@ -34,7 +34,6 @@
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS

42
arch/arm/cpu/armv7/s5p-common/pwm.c
View file

@ -70,7 +70,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
return tin_parent_rate / 16;
}
#define NS_IN_HZ (1000000000UL)
#define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
@ -79,7 +79,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
unsigned int offset;
unsigned long tin_rate;
unsigned long tin_ns;
unsigned long period;
unsigned long frequency;
unsigned long tcon;
unsigned long tcnt;
unsigned long tcmp;
@ -89,34 +89,24 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
* fact that anything faster than 1GHz is easily representable
* by 32bits.
*/
if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
period = NS_IN_HZ / period_ns;
frequency = NS_IN_SEC / period_ns;
/* Check to see if we are changing the clock rate of the PWM */
tin_rate = pwm_calc_tin(pwm_id, period);
tin_rate = pwm_calc_tin(pwm_id, frequency);
tin_ns = NS_IN_HZ / tin_rate;
tin_ns = NS_IN_SEC / tin_rate;
tcnt = period_ns / tin_ns;
/* Note, counters count down */
tcmp = duty_ns / tin_ns;
tcmp = tcnt - tcmp;
/*
* the pwm hw only checks the compare register after a decrement,
* so the pin never toggles if tcmp = tcnt
*/
if (tcmp == tcnt)
tcmp--;
if (tcmp < 0)
tcmp = 0;
/* Update the PWM register block. */
offset = pwm_id * 3;
if (pwm_id < 4) {
@ -143,7 +133,7 @@ int pwm_init(int pwm_id, int div, int invert)
u32 val;
const struct s5p_timer *pwm =
(struct s5p_timer *)samsung_get_base_timer();
unsigned long timer_rate_hz;
unsigned long ticks_per_period;
unsigned int offset, prescaler;
/*
@ -167,14 +157,24 @@ int pwm_init(int pwm_id, int div, int invert)
val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
writel(val, &pwm->tcfg1);
timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
(div + 1));
if (pwm_id == 4) {
/*
* TODO(sjg): Use this as a countdown timer for now. We count
* down from the maximum value to 0, then reset.
*/
ticks_per_period = -1UL;
} else {
const unsigned long pwm_hz = 1000;
unsigned long timer_rate_hz = get_pwm_clk() /
((prescaler + 1) * (1 << div));
timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
ticks_per_period = timer_rate_hz / pwm_hz;
}
/* set count value */
offset = pwm_id * 3;
writel(timer_rate_hz, &pwm->tcntb0 + offset);
writel(ticks_per_period, &pwm->tcntb0 + offset);
val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
if (invert && (pwm_id < 4))

115
arch/arm/cpu/armv7/s5p-common/timer.c
View file

@ -39,13 +39,33 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
return (struct s5p_timer *)samsung_get_base_timer();
}
/**
* Read the countdown timer.
*
* This operates at 1MHz and counts downwards. It will wrap about every
* hour (2^32 microseconds).
*
* @return current value of timer
*/
static unsigned long timer_get_us_down(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
return readl(&timer->tcnto4);
}
int timer_init(void)
{
/* PWM Timer 4 */
pwm_init(4, MUX_DIV_2, 0);
pwm_config(4, 0, 0);
pwm_init(4, MUX_DIV_4, 0);
pwm_config(4, 100000, 100000);
pwm_enable(4);
/* Use this as the current monotonic time in us */
gd->arch.timer_reset_value = 0;
/* Use this as the last timer value we saw */
gd->arch.lastinc = timer_get_us_down();
reset_timer_masked();
return 0;
@ -56,48 +76,43 @@ int timer_init(void)
*/
unsigned long get_timer(unsigned long base)
{
return get_timer_masked() - base;
ulong now = timer_get_us_down();
/*
* Increment the time by the amount elapsed since the last read.
* The timer may have wrapped around, but it makes no difference to
* our arithmetic here.
*/
gd->arch.timer_reset_value += gd->arch.lastinc - now;
gd->arch.lastinc = now;
/* Divide by 1000 to convert from us to ms */
return gd->arch.timer_reset_value / 1000 - base;
}
unsigned long timer_get_us(void)
{
static unsigned long base_time_us;
struct s5p_timer *const timer =
(struct s5p_timer *)samsung_get_base_timer();
unsigned long now_downward_us = readl(&timer->tcnto4);
if (!base_time_us)
base_time_us = now_downward_us;
/* Note that this timer counts downward. */
return base_time_us - now_downward_us;
}
/* delay x useconds */
void __udelay(unsigned long usec)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long tmo, tmp, count_value;
unsigned long count_value;
count_value = readl(&timer->tcntb4);
if (usec >= 1000) {
/*
* if "big" number, spread normalization
* to seconds
* 1. start to normalize for usec to ticks per sec
* 2. find number of "ticks" to wait to achieve target
* 3. finish normalize.
*/
tmo = usec / 1000;
tmo *= (CONFIG_SYS_HZ * count_value);
tmo /= 1000;
} else {
/* else small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ * count_value;
tmo /= (1000 * 1000);
}
/* get current timestamp */
tmp = get_current_tick();
/* if setting this fordward will roll time stamp */
/* reset "advancing" timestamp to 0, set lastinc value */
/* else, set advancing stamp wake up time */
if ((tmo + tmp + 1) < tmp)
reset_timer_masked();
else
tmo += tmp;
/* loop till event */
while (get_current_tick() < tmo)
; /* nop */
count_value = timer_get_us_down();
while ((int)(count_value - timer_get_us_down()) < (int)usec)
;
}
void reset_timer_masked(void)
@ -109,30 +124,6 @@ void reset_timer_masked(void)
gd->arch.tbl = 0;
}
unsigned long get_timer_masked(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long count_value = readl(&timer->tcntb4);
return get_current_tick() / count_value;
}
unsigned long get_current_tick(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now = readl(&timer->tcnto4);
unsigned long count_value = readl(&timer->tcntb4);
if (gd->arch.lastinc >= now)
gd->arch.tbl += gd->arch.lastinc - now;
else
gd->arch.tbl += gd->arch.lastinc + count_value - now;
gd->arch.lastinc = now;
return gd->arch.tbl;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.

2
arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
View file

@ -27,7 +27,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
arch/arm/cpu/armv7/start.o (.text)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sdram

29
arch/arm/cpu/armv7/start.S
View file

@ -81,7 +81,11 @@ _end_vect:
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -90,9 +94,9 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.global _image_copy_end_ofs
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
@ -161,28 +165,23 @@ reset:
#ifndef CONFIG_SPL_BUILD
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
ENTRY(relocate_code)
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -190,7 +189,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -465,9 +463,10 @@ ENDPROC(cpu_init_crit)
@ spots for abort stack
str lr, [r0] @ save caller lr in position 0
@ of saved stack
mrs r0, spsr @ get the spsr
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of
@ saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm

28
arch/arm/cpu/ixp/start.S
View file

@ -98,7 +98,11 @@ _fiq: .word fiq
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -110,6 +114,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -250,29 +258,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -281,7 +284,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

16
arch/arm/cpu/ixp/u-boot.lds
View file

@ -54,6 +54,8 @@ SECTIONS
. = ALIGN(4);
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
@ -67,17 +69,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

29
arch/arm/cpu/pxa/start.S
View file

@ -102,7 +102,7 @@ _end_vect:
.globl _TEXT_BASE
_TEXT_BASE:
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
@ -118,6 +118,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -169,17 +173,13 @@ reset:
/*------------------------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
/* Disable the Dcache RAM lock for stack now */
#ifdef CONFIG_CPU_PXA25X
@ -189,16 +189,15 @@ relocate_code:
#endif
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -207,7 +206,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
@ -387,8 +385,9 @@ cpu_init_crit:
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm

28
arch/arm/cpu/s3c44b0/start.S
View file

@ -64,7 +64,11 @@ _start: b reset
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -76,6 +80,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -133,29 +141,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -164,7 +167,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

28
arch/arm/cpu/sa1100/start.S
View file

@ -74,7 +74,11 @@ _fiq: .word fiq
.globl _TEXT_BASE
_TEXT_BASE:
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
/*
* These are defined in the board-specific linker script.
@ -86,6 +90,10 @@ _TEXT_BASE:
_bss_start_ofs:
.word __bss_start - _start
.globl _image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
@ -137,29 +145,24 @@ reset:
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
mov r6, r0 /* save addr of destination */
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r10-r11} /* copy from source address [r0] */
stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
@ -168,7 +171,6 @@ copy_loop:
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */

24
arch/arm/cpu/u-boot-spl.lds
View file

@ -65,15 +65,6 @@ SECTIONS
_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
@ -88,6 +79,17 @@ SECTIONS
/DISCARD/ : { *(.gnu*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#if defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif
#if defined(CONFIG_SPL_MAX_FOOTPRINT)
ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
"SPL image plus BSS too big");
#endif

18
arch/arm/cpu/u-boot.lds
View file

@ -81,18 +81,24 @@ SECTIONS
*(.mmutable)
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }
@ -101,7 +107,3 @@ SECTIONS
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#endif

13
arch/arm/dts/exynos5250.dtsi
View file

@ -156,4 +156,17 @@
reg = <0x10060000 0x10000>;
};
fimd@14400000 {
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

18
arch/arm/imx-common/Makefile
View file

@ -32,6 +32,7 @@ COBJS-y = iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@ -54,6 +55,23 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONF
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
rm $(OBJTREE)/spl/u-boot-spl-pad.imx
$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
(echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \
cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
$(OBJTREE)/spl/u-boot-nand-spl-pad.imx
rm $(OBJTREE)/spl/u-boot-nand-spl.imx
cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
#########################################################################

32
drivers/usb/host/s3c64xx-hcd.c → arch/arm/imx-common/cmd_hdmidet.c
View file

@ -1,8 +1,5 @@
/*
* URB OHCI HCD (Host Controller Driver) initialization for USB on the S3C64XX.
*
* Copyright (C) 2008,
* Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de>
* Copyright (C) 2012 Boundary Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,25 +18,20 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/s3c6400.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/io.h>
int usb_cpu_init(void)
static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
OTHERS_REG |= 0x10000;
return 0;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
return (reg&HDMI_PHY_HPD) ? 0 : 1;
}
int usb_cpu_stop(void)
{
OTHERS_REG &= ~0x10000;
return 0;
}
void usb_cpu_init_fail(void)
{
OTHERS_REG &= ~0x10000;
}
U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
"detect HDMI monitor",
""
);

26
arch/arm/imx-common/timer.c
View file

@ -48,9 +48,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
@ -70,7 +67,6 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
int timer_init(void)
{
int i;
ulong val;
/* setup GP Timer 1 */
__raw_writel(GPTCR_SWR, &cur_gpt->control);
@ -85,9 +81,8 @@ int timer_init(void)
i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
gd->arch.tbl = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
return 0;
}
@ -96,18 +91,11 @@ unsigned long long get_ticks(void)
{
ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
/* increment tbu if tbl has rolled over */
if (now < gd->arch.tbl)
gd->arch.tbu++;
gd->arch.tbl = now;
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong get_timer_masked(void)

22
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View file

@ -84,20 +84,20 @@
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
/* Micron MT41K256M16HA-125E */
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x40
#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
#define MT41K256M16HA125E_RD_DQS 0x3C
#define MT41K256M16HA125E_WR_DQS 0x45
#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
#define MT41K256M16HA125E_RD_DQS 0x38
#define MT41K256M16HA125E_WR_DQS 0x44
#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */

58
arch/arm/include/asm/arch-am33xx/omap_gpmc.h
View file

@ -23,63 +23,7 @@
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define ECCCLEAR (0x1 << 8)
#define ECCRESULTREG1 (0x1 << 0)
#define ECCSIZE512BYTE 0xFF
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
#define ECCSIZE0SEL (0x000 << 0)
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
9, 10, 11, 12},\
.oobfree = {\
{.offset = 13,\
.length = 51 } } \
}
#endif
/* Large Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13},\
.oobfree = {\
{.offset = 14,\
.length = 50 } } \
}
#endif
/* Small Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {1, 2, 3},\
.oobfree = {\
{.offset = 4,\
.length = 12 } } \
}
#endif
/* Small Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {2, 3, 4},\
.oobfree = {\
{.offset = 5,\
.length = 11 } } \
}
#endif
/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
.eccbytes = 32,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\

8
arch/arm/include/asm/arch-am33xx/spl.h
View file

@ -37,4 +37,12 @@
#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#ifdef CONFIG_AM33XX
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
#elif defined(CONFIG_TI814X)
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#endif
#endif

2
arch/arm/include/asm/arch-am33xx/sys_proto.h
View file

@ -39,5 +39,5 @@ struct gpmc_cs;
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
void omap_nand_switch_ecc(int);
void omap_nand_switch_ecc(uint32_t, uint32_t);
#endif

2
arch/arm/include/asm/arch-bcm2835/timer.h
View file

@ -34,4 +34,6 @@ struct bcm2835_timer_regs {
#define BCM2835_TIMER_CS_M1 (1 << 1)
#define BCM2835_TIMER_CS_M0 (1 << 0)
extern ulong get_timer_us(ulong base);
#endif

15
arch/arm/include/asm/arch-exynos/clk.h
View file

@ -29,6 +29,12 @@
#define VPLL 4
#define BPLL 5
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
EXYNOS_SRC_VPLL,
};
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
/**
* get the clk frequency of the required peripheral
*
* @param peripheral Peripheral id
*
* @return frequency of the peripheral clk
*/
unsigned long clock_get_periph_rate(int peripheral);
#endif

10
arch/arm/include/asm/arch-exynos/cpu.h
View file

@ -62,6 +62,7 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
@ -92,9 +93,10 @@
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
@ -106,6 +108,7 @@
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
@ -205,6 +208,7 @@ static inline unsigned int samsung_get_base_##device(void) \
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)

1
arch/arm/include/asm/arch-exynos/dp_info.h
View file

@ -199,7 +199,6 @@ enum {
struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info;
void (*phy_enable)(unsigned int);
};
#ifdef CONFIG_EXYNOS_DP

5
arch/arm/include/asm/arch-exynos/periph.h
View file

@ -61,6 +61,11 @@ enum periph_id {
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SDMMC4,
PERIPH_ID_PWM0,
PERIPH_ID_PWM1,
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,

1
arch/arm/include/asm/arch-mx5/imx-regs.h
View file

@ -230,6 +230,7 @@
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

1
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -346,6 +346,7 @@ struct cspi_regs {
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

3
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
View file

@ -50,6 +50,8 @@
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
@ -90,6 +92,7 @@ enum {
MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),

6
arch/arm/include/asm/arch-omap24xx/omap2420.h
View file

@ -212,9 +212,9 @@
# define H4_CS1_BASE 0x04000000 /* debug board */
# define H4_CS2_BASE 0x0A000000 /* wifi board */
#else
# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
# define H4_CS1_BASE 0x08000000 /* debug board */
# define H4_CS2_BASE 0x0A000000 /* wifi board */
# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
# define H4_CS1_BASE 0x04000000 /* debug board */
# define H4_CS2_BASE 0x0C000000 /* wifi board */
#endif
/* base address for indirect vectors (internal boot mode) */

6
arch/arm/include/asm/arch-omap3/cpu.h
View file

@ -109,6 +109,10 @@ struct gpmc_cs {
u8 res[8]; /* blow up to 0x30 byte */
};
struct bch_res_0_3 {
u32 bch_result_x[4];
};
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
@ -135,6 +139,8 @@ struct gpmc {
u32 ecc7_result; /* 0x218 */
u32 ecc8_result; /* 0x21C */
u32 ecc9_result; /* 0x220 */
u8 res7[0x1C]; /* fill up to 0x240 */
struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
};
/* Used for board specific gpmc initialization */

68
arch/arm/include/asm/arch-omap3/omap_gpmc.h
View file

@ -23,62 +23,22 @@
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define ECCCLEAR (0x1 << 8)
#define ECCRESULTREG1 (0x1 << 0)
#define ECCSIZE512BYTE 0xFF
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
#define ECCSIZE0SEL (0x000 << 0)
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
9, 10, 11, 12},\
/*
* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
* The OOB layout was first defined by linx kernel in commit
* 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
* we want to be compatible.
*/
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
.eccbytes = 56,\
.eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
.oobfree = {\
{.offset = 13,\
.length = 51 } } \
{.offset = 2,\
.length = 10 } } \
}
#endif
/* Large Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13},\
.oobfree = {\
{.offset = 14,\
.length = 50 } } \
}
#endif
/* Small Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {1, 2, 3},\
.oobfree = {\
{.offset = 4,\
.length = 12 } } \
}
#endif
/* Small Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {2, 3, 4},\
.oobfree = {\
{.offset = 5,\
.length = 11 } } \
}
#endif
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
#define NET_LAN9221_GPMC_CONFIG1 0x00001000

3
arch/arm/include/asm/arch-omap3/spl.h
View file

@ -31,4 +31,7 @@
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7
#define BOOT_DEVICE_MMC2_2 0xFF
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#endif

2
arch/arm/include/asm/arch-omap3/sys_proto.h
View file

@ -78,7 +78,7 @@ void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(int);
void omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void dieid_num_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);

1
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -147,7 +147,6 @@ struct s32ktimer {
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)

2
arch/arm/include/asm/arch-omap4/spl.h
View file

@ -32,4 +32,6 @@
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 0xFF
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
#endif

1
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -196,7 +196,6 @@ struct s32ktimer {
* SRAM scratch space entries
*/
#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)

2
arch/arm/include/asm/arch-omap5/spl.h
View file

@ -32,4 +32,6 @@
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
#endif

63
arch/arm/include/asm/arch-s3c64xx/hardware.h
View file

@ -1,63 +0,0 @@
/*
* Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ARCH_HARDWARE_H_
#define _ARCH_HARDWARE_H_
#include <asm/sizes.h>
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#define __REG(x) (*(vu_long *)(x))
#define __REGl(x) (*(vu_long *)(x))
#define __REGw(x) (*(vu_short *)(x))
#define __REGb(x) (*(vu_char *)(x))
#define __REG2(x, y) (*(vu_long *)((x) + (y)))
#else
#define UData(Data) (Data)
#define __REG(x) (x)
#define __REGl(x) (x)
#define __REGw(x) (x)
#define __REGb(x) (x)
#define __REG2(x, y) ((x) + (y))
#endif
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* _ARCH_HARDWARE_H_ */

895
arch/arm/include/asm/arch-s3c64xx/s3c6400.h
View file

@ -1,895 +0,0 @@
/*
* (C) Copyright 2007
* Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
* - only support for S3C6400
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : s3c6400.h
*
* Based on S3C6400 User's manual Rev 0.0
************************************************/
#ifndef __S3C6400_H__
#define __S3C6400_H__
#define S3C64XX_UART_CHANNELS 3
#define S3C64XX_SPI_CHANNELS 2
#include <asm/hardware.h>
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
/* Clock & Power Controller for mDirac3*/
#define APLL_LOCK_OFFSET 0x00
#define MPLL_LOCK_OFFSET 0x04
#define EPLL_LOCK_OFFSET 0x08
#define APLL_CON_OFFSET 0x0C
#define MPLL_CON_OFFSET 0x10
#define EPLL_CON0_OFFSET 0x14
#define EPLL_CON1_OFFSET 0x18
#define CLK_SRC_OFFSET 0x1C
#define CLK_DIV0_OFFSET 0x20
#define CLK_DIV1_OFFSET 0x24
#define CLK_DIV2_OFFSET 0x28
#define CLK_OUT_OFFSET 0x2C
#define HCLK_GATE_OFFSET 0x30
#define PCLK_GATE_OFFSET 0x34
#define SCLK_GATE_OFFSET 0x38
#define AHB_CON0_OFFSET 0x100
#define AHB_CON1_OFFSET 0x104
#define AHB_CON2_OFFSET 0x108
#define SELECT_DMA_OFFSET 0x110
#define SW_RST_OFFSET 0x114
#define SYS_ID_OFFSET 0x118
#define MEM_SYS_CFG_OFFSET 0x120
#define QOS_OVERRIDE0_OFFSET 0x124
#define QOS_OVERRIDE1_OFFSET 0x128
#define MEM_CFG_STAT_OFFSET 0x12C
#define PWR_CFG_OFFSET 0x804
#define EINT_MASK_OFFSET 0x808
#define NOR_CFG_OFFSET 0x810
#define STOP_CFG_OFFSET 0x814
#define SLEEP_CFG_OFFSET 0x818
#define OSC_FREQ_OFFSET 0x820
#define OSC_STABLE_OFFSET 0x824
#define PWR_STABLE_OFFSET 0x828
#define FPC_STABLE_OFFSET 0x82C
#define MTC_STABLE_OFFSET 0x830
#define OTHERS_OFFSET 0x900
#define RST_STAT_OFFSET 0x904
#define WAKEUP_STAT_OFFSET 0x908
#define BLK_PWR_STAT_OFFSET 0x90C
#define INF_REG0_OFFSET 0xA00
#define INF_REG1_OFFSET 0xA04
#define INF_REG2_OFFSET 0xA08
#define INF_REG3_OFFSET 0xA0C
#define INF_REG4_OFFSET 0xA10
#define INF_REG5_OFFSET 0xA14
#define INF_REG6_OFFSET 0xA18
#define INF_REG7_OFFSET 0xA1C
#define OSC_CNT_VAL_OFFSET 0x824
#define PWR_CNT_VAL_OFFSET 0x828
#define FPC_CNT_VAL_OFFSET 0x82C
#define MTC_CNT_VAL_OFFSET 0x830
#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
SELECT_DMA_OFFSET)
#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
MEM_SYS_CFG_OFFSET)
#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
QOS_OVERRIDE0_OFFSET)
#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
QOS_OVERRIDE1_OFFSET)
#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
MEM_CFG_STAT_OFFSET)
#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
OSC_CNT_VAL_OFFSET)
#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
PWR_CNT_VAL_OFFSET)
#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
FPC_CNT_VAL_OFFSET)
#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
MTC_CNT_VAL_OFFSET)
#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
WAKEUP_STAT_OFFSET)
#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
BLK_PWR_STAT_OFFSET)
#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
/*
* GPIO
*/
#define ELFIN_GPIO_BASE 0x7f008000
#define GPACON_OFFSET 0x00
#define GPADAT_OFFSET 0x04
#define GPAPUD_OFFSET 0x08
#define GPACONSLP_OFFSET 0x0C
#define GPAPUDSLP_OFFSET 0x10
#define GPBCON_OFFSET 0x20
#define GPBDAT_OFFSET 0x24
#define GPBPUD_OFFSET 0x28
#define GPBCONSLP_OFFSET 0x2C
#define GPBPUDSLP_OFFSET 0x30
#define GPCCON_OFFSET 0x40
#define GPCDAT_OFFSET 0x44
#define GPCPUD_OFFSET 0x48
#define GPCCONSLP_OFFSET 0x4C
#define GPCPUDSLP_OFFSET 0x50
#define GPDCON_OFFSET 0x60
#define GPDDAT_OFFSET 0x64
#define GPDPUD_OFFSET 0x68
#define GPDCONSLP_OFFSET 0x6C
#define GPDPUDSLP_OFFSET 0x70
#define GPECON_OFFSET 0x80
#define GPEDAT_OFFSET 0x84
#define GPEPUD_OFFSET 0x88
#define GPECONSLP_OFFSET 0x8C
#define GPEPUDSLP_OFFSET 0x90
#define GPFCON_OFFSET 0xA0
#define GPFDAT_OFFSET 0xA4
#define GPFPUD_OFFSET 0xA8
#define GPFCONSLP_OFFSET 0xAC
#define GPFPUDSLP_OFFSET 0xB0
#define GPGCON_OFFSET 0xC0
#define GPGDAT_OFFSET 0xC4
#define GPGPUD_OFFSET 0xC8
#define GPGCONSLP_OFFSET 0xCC
#define GPGPUDSLP_OFFSET 0xD0
#define GPHCON0_OFFSET 0xE0
#define GPHCON1_OFFSET 0xE4
#define GPHDAT_OFFSET 0xE8
#define GPHPUD_OFFSET 0xEC
#define GPHCONSLP_OFFSET 0xF0
#define GPHPUDSLP_OFFSET 0xF4
#define GPICON_OFFSET 0x100
#define GPIDAT_OFFSET 0x104
#define GPIPUD_OFFSET 0x108
#define GPICONSLP_OFFSET 0x10C
#define GPIPUDSLP_OFFSET 0x110
#define GPJCON_OFFSET 0x120
#define GPJDAT_OFFSET 0x124
#define GPJPUD_OFFSET 0x128
#define GPJCONSLP_OFFSET 0x12C
#define GPJPUDSLP_OFFSET 0x130
#define MEM0DRVCON_OFFSET 0x1D0
#define MEM1DRVCON_OFFSET 0x1D4
#define GPKCON0_OFFSET 0x800
#define GPKCON1_OFFSET 0x804
#define GPKDAT_OFFSET 0x808
#define GPKPUD_OFFSET 0x80C
#define GPLCON0_OFFSET 0x810
#define GPLCON1_OFFSET 0x814
#define GPLDAT_OFFSET 0x818
#define GPLPUD_OFFSET 0x81C
#define GPMCON_OFFSET 0x820
#define GPMDAT_OFFSET 0x824
#define GPMPUD_OFFSET 0x828
#define GPNCON_OFFSET 0x830
#define GPNDAT_OFFSET 0x834
#define GPNPUD_OFFSET 0x838
#define GPOCON_OFFSET 0x140
#define GPODAT_OFFSET 0x144
#define GPOPUD_OFFSET 0x148
#define GPOCONSLP_OFFSET 0x14C
#define GPOPUDSLP_OFFSET 0x150
#define GPPCON_OFFSET 0x160
#define GPPDAT_OFFSET 0x164
#define GPPPUD_OFFSET 0x168
#define GPPCONSLP_OFFSET 0x16C
#define GPPPUDSLP_OFFSET 0x170
#define GPQCON_OFFSET 0x180
#define GPQDAT_OFFSET 0x184
#define GPQPUD_OFFSET 0x188
#define GPQCONSLP_OFFSET 0x18C
#define GPQPUDSLP_OFFSET 0x190
#define EINTPEND_OFFSET 0x924
#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
/*
* Bus Matrix
*/
#define ELFIN_MEM_SYS_CFG 0x7e00f120
#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
/*
* Memory controller
*/
#define ELFIN_SROM_BASE 0x70000000
#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
/*
* SDRAM Controller
*/
#define ELFIN_DMC0_BASE 0x7e000000
#define ELFIN_DMC1_BASE 0x7e001000
#define INDEX_DMC_MEMC_STATUS 0x00
#define INDEX_DMC_MEMC_CMD 0x04
#define INDEX_DMC_DIRECT_CMD 0x08
#define INDEX_DMC_MEMORY_CFG 0x0C
#define INDEX_DMC_REFRESH_PRD 0x10
#define INDEX_DMC_CAS_LATENCY 0x14
#define INDEX_DMC_T_DQSS 0x18
#define INDEX_DMC_T_MRD 0x1C
#define INDEX_DMC_T_RAS 0x20
#define INDEX_DMC_T_RC 0x24
#define INDEX_DMC_T_RCD 0x28
#define INDEX_DMC_T_RFC 0x2C
#define INDEX_DMC_T_RP 0x30
#define INDEX_DMC_T_RRD 0x34
#define INDEX_DMC_T_WR 0x38
#define INDEX_DMC_T_WTR 0x3C
#define INDEX_DMC_T_XP 0x40
#define INDEX_DMC_T_XSR 0x44
#define INDEX_DMC_T_ESR 0x48
#define INDEX_DMC_MEMORY_CFG2 0x4C
#define INDEX_DMC_CHIP_0_CFG 0x200
#define INDEX_DMC_CHIP_1_CFG 0x204
#define INDEX_DMC_CHIP_2_CFG 0x208
#define INDEX_DMC_CHIP_3_CFG 0x20C
#define INDEX_DMC_USER_STATUS 0x300
#define INDEX_DMC_USER_CONFIG 0x304
/*
* Memory Chip direct command
*/
#define DMC_NOP0 0x0c0000
#define DMC_NOP1 0x1c0000
#define DMC_PA0 0x000000 /* Precharge all */
#define DMC_PA1 0x100000
#define DMC_AR0 0x040000 /* Autorefresh */
#define DMC_AR1 0x140000
#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
#define DMC_SDR_MR1 0x180032
#define DMC_DDR_MR0 0x080162
#define DMC_DDR_MR1 0x180162
#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
#define DMC_mDDR_MR1 0x180032
#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
#define DMC_mSDR_EMR1 0x1a0000
#define DMC_DDR_EMR0 0x090000
#define DMC_DDR_EMR1 0x190000
#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
#define DMC_mDDR_EMR1 0x1a0000
/*
* Definitions for memory configuration
* Set memory configuration
* active_chips = 1'b0 (1 chip)
* qos_master_chip = 3'b000(ARID[3:0])
* memory burst = 3'b010(burst 4)
* stop_mem_clock = 1'b0(disable dynamical stop)
* auto_power_down = 1'b0(disable auto power-down mode)
* power_down_prd = 6'b00_0000(0 cycle for auto power-down)
* ap_bit = 1'b0 (bit position of auto-precharge is 10)
* row_bits = 3'b010(# row address 13)
* column_bits = 3'b010(# column address 10 )
*
* Set user configuration
* 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
*
* Set chip select for chip [n]
* row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
* CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
*/
/*
* Nand flash controller
*/
#define ELFIN_NAND_BASE 0x70200000
#define NFCONF_OFFSET 0x00
#define NFCONT_OFFSET 0x04
#define NFCMMD_OFFSET 0x08
#define NFADDR_OFFSET 0x0c
#define NFDATA_OFFSET 0x10
#define NFMECCDATA0_OFFSET 0x14
#define NFMECCDATA1_OFFSET 0x18
#define NFSECCDATA0_OFFSET 0x1c
#define NFSBLK_OFFSET 0x20
#define NFEBLK_OFFSET 0x24
#define NFSTAT_OFFSET 0x28
#define NFESTAT0_OFFSET 0x2c
#define NFESTAT1_OFFSET 0x30
#define NFMECC0_OFFSET 0x34
#define NFMECC1_OFFSET 0x38
#define NFSECC_OFFSET 0x3c
#define NFMLCBITPT_OFFSET 0x40
#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
#define NFCONF_ECC_4BIT (1<<24)
#define NFCONT_ECC_ENC (1<<18)
#define NFCONT_WP (1<<16)
#define NFCONT_MECCLOCK (1<<7)
#define NFCONT_SECCLOCK (1<<6)
#define NFCONT_INITMECC (1<<5)
#define NFCONT_INITSECC (1<<4)
#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
#define NFCONT_CS_ALT (1<<2)
#define NFCONT_CS (1<<1)
#define NFCONT_ENABLE (1<<0)
#define NFSTAT_ECCENCDONE (1<<7)
#define NFSTAT_ECCDECDONE (1<<6)
#define NFSTAT_RnB (1<<0)
#define NFESTAT0_ECCBUSY (1<<31)
/*
* Interrupt
*/
#define ELFIN_VIC0_BASE_ADDR 0x71200000
#define ELFIN_VIC1_BASE_ADDR 0x71300000
#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
#define oVECTADDR 0xF00 /* VIC ADDRESS */
/*
* Watchdog timer
*/
#define ELFIN_WATCHDOG_BASE 0x7E004000
#define WTCON_REG __REG(0x7E004004)
#define WTDAT_REG __REG(0x7E004008)
#define WTCNT_REG __REG(0x7E00400C)
/*
* UART
*/
#define ELFIN_UART_BASE 0x7F005000
#define ELFIN_UART0_OFFSET 0x0000
#define ELFIN_UART1_OFFSET 0x0400
#define ELFIN_UART2_OFFSET 0x0800
#define ULCON_OFFSET 0x00
#define UCON_OFFSET 0x04
#define UFCON_OFFSET 0x08
#define UMCON_OFFSET 0x0C
#define UTRSTAT_OFFSET 0x10
#define UERSTAT_OFFSET 0x14
#define UFSTAT_OFFSET 0x18
#define UMSTAT_OFFSET 0x1C
#define UTXH_OFFSET 0x20
#define URXH_OFFSET 0x24
#define UBRDIV_OFFSET 0x28
#define UDIVSLOT_OFFSET 0x2C
#define UINTP_OFFSET 0x30
#define UINTSP_OFFSET 0x34
#define UINTM_OFFSET 0x38
#define ULCON0_REG __REG(0x7F005000)
#define UCON0_REG __REG(0x7F005004)
#define UFCON0_REG __REG(0x7F005008)
#define UMCON0_REG __REG(0x7F00500C)
#define UTRSTAT0_REG __REG(0x7F005010)
#define UERSTAT0_REG __REG(0x7F005014)
#define UFSTAT0_REG __REG(0x7F005018)
#define UMSTAT0_REG __REG(0x7F00501c)
#define UTXH0_REG __REG(0x7F005020)
#define URXH0_REG __REG(0x7F005024)
#define UBRDIV0_REG __REG(0x7F005028)
#define UDIVSLOT0_REG __REG(0x7F00502c)
#define UINTP0_REG __REG(0x7F005030)
#define UINTSP0_REG __REG(0x7F005034)
#define UINTM0_REG __REG(0x7F005038)
#define ULCON1_REG __REG(0x7F005400)
#define UCON1_REG __REG(0x7F005404)
#define UFCON1_REG __REG(0x7F005408)
#define UMCON1_REG __REG(0x7F00540C)
#define UTRSTAT1_REG __REG(0x7F005410)
#define UERSTAT1_REG __REG(0x7F005414)
#define UFSTAT1_REG __REG(0x7F005418)
#define UMSTAT1_REG __REG(0x7F00541c)
#define UTXH1_REG __REG(0x7F005420)
#define URXH1_REG __REG(0x7F005424)
#define UBRDIV1_REG __REG(0x7F005428)
#define UDIVSLOT1_REG __REG(0x7F00542c)
#define UINTP1_REG __REG(0x7F005430)
#define UINTSP1_REG __REG(0x7F005434)
#define UINTM1_REG __REG(0x7F005438)
#define UTRSTAT_TX_EMPTY (1 << 2)
#define UTRSTAT_RX_READY (1 << 0)
#define UART_ERR_MASK 0xF
/*
* PWM timer
*/
#define ELFIN_TIMER_BASE 0x7F006000
#define TCFG0_REG __REG(0x7F006000)
#define TCFG1_REG __REG(0x7F006004)
#define TCON_REG __REG(0x7F006008)
#define TCNTB0_REG __REG(0x7F00600c)
#define TCMPB0_REG __REG(0x7F006010)
#define TCNTO0_REG __REG(0x7F006014)
#define TCNTB1_REG __REG(0x7F006018)
#define TCMPB1_REG __REG(0x7F00601c)
#define TCNTO1_REG __REG(0x7F006020)
#define TCNTB2_REG __REG(0x7F006024)
#define TCMPB2_REG __REG(0x7F006028)
#define TCNTO2_REG __REG(0x7F00602c)
#define TCNTB3_REG __REG(0x7F006030)
#define TCMPB3_REG __REG(0x7F006034)
#define TCNTO3_REG __REG(0x7F006038)
#define TCNTB4_REG __REG(0x7F00603c)
#define TCNTO4_REG __REG(0x7F006040)
/* Fields */
#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
#define fTCFG1_MUX4 Fld(4, 16)
/* bits */
#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON (TCON_4_ONOFF * 1)
#define COUNT_4_OFF (TCON_4_ONOFF * 0)
#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
#define TIMER3_MANUP (TCON_3_MAN*1)
#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
#define TIMER3_ON (TCON_3_ONOFF * 1)
#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
#if defined(CONFIG_CLK_400_100_50)
#define STARTUP_AMDIV 400
#define STARTUP_MDIV 400
#define STARTUP_PDIV 6
#define STARTUP_SDIV 1
#elif defined(CONFIG_CLK_400_133_66)
#define STARTUP_AMDIV 400
#define STARTUP_MDIV 533
#define STARTUP_PDIV 6
#define STARTUP_SDIV 1
#elif defined(CONFIG_CLK_533_133_66)
#define STARTUP_AMDIV 533
#define STARTUP_MDIV 533
#define STARTUP_PDIV 6
#define STARTUP_SDIV 1
#elif defined(CONFIG_CLK_667_133_66)
#define STARTUP_AMDIV 667
#define STARTUP_MDIV 533
#define STARTUP_PDIV 6
#define STARTUP_SDIV 1
#endif
#define STARTUP_PCLKDIV 3
#define STARTUP_HCLKX2DIV 1
#define STARTUP_HCLKDIV 1
#define STARTUP_MPLLDIV 1
#define STARTUP_APLLDIV 0
#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
(STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
(STARTUP_PDIV << 8) | STARTUP_SDIV)
#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
STARTUP_PDIV) * STARTUP_MDIV)
#if defined(CONFIG_SYNC_MODE)
#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
(STARTUP_PDIV << 8) | STARTUP_SDIV)
#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
STARTUP_PDIV) * STARTUP_MDIV)
#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
(STARTUP_HCLKDIV + 1))
#else
#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
(STARTUP_PDIV << 8) | STARTUP_SDIV)
#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
STARTUP_PDIV) * STARTUP_AMDIV)
#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
(STARTUP_HCLKDIV + 1))
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */
#define DMC1_MEM_CFG2 0xB45
#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
/* DDR Parameters */
#define DDR_tREFRESH 7800 /* ns */
#define DDR_tRAS 45 /* ns (min: 45ns)*/
#define DDR_tRC 68 /* ns (min: 67.5ns)*/
#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
#define DDR_tRFC 80 /* ns (min: 80ns)*/
#define DDR_tRP 23 /* ns (min: 22.5ns)*/
#define DDR_tRRD 15 /* ns (min: 15ns)*/
#define DDR_tWR 15 /* ns (min: 15ns)*/
#define DDR_tXSR 120 /* ns (min: 120ns)*/
#define DDR_CASL 3 /* CAS Latency 3 */
/*
* mDDR memory configuration
*/
#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
#define DMC_DDR_BA_EMRS 2
#define DMC_DDR_MEM_CASLAT 3
/* 6 Set Cas Latency to 3 */
#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
/* Min 0.75 ~ 1.25 */
#define DMC_DDR_t_DQSS 1
/* Min 2 tck */
#define DMC_DDR_t_MRD 2
/* 7, Min 45ns */
#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
/* 10, Min 67.5ns */
#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
/* 4,5(TRM), Min 22.5ns */
#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
/* 11,18(TRM) Min 80ns */
#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
/* 4, 5(TRM) Min 22.5ns */
#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
/* 3, Min 15ns */
#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
/* Min 15ns */
#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
#define DMC_DDR_t_WTR 2
/* 1tck + tIS(1.5ns) */
#define DMC_DDR_t_XP 2
/* 17, Min 120ns */
#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
#define DMC_DDR_t_ESR DMC_DDR_t_XSR
/* TRM 2656 */
#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
/* 2b01 : mDDR */
#define DMC_DDR_USER_CONFIG 1
#ifndef __ASSEMBLY__
enum s3c64xx_uarts_nr {
S3C64XX_UART0,
S3C64XX_UART1,
S3C64XX_UART2,
};
#include "s3c64x0.h"
static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
{
return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
}
#endif
#endif /*__S3C6400_H__*/

90
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
View file

@ -1,90 +0,0 @@
/*
* (C) Copyright 2003
* David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : S3C64XX.h
* Version : 31.3.2003
*
* common stuff for SAMSUNG S3C64XX SoC
************************************************/
#ifndef __S3C64XX_H__
#define __S3C64XX_H__
#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
#endif
#include <asm/types.h>
/* UART (see manual chapter 11) */
typedef struct {
volatile u32 ULCON;
volatile u32 UCON;
volatile u32 UFCON;
volatile u32 UMCON;
volatile u32 UTRSTAT;
volatile u32 UERSTAT;
volatile u32 UFSTAT;
volatile u32 UMSTAT;
#ifdef __BIG_ENDIAN
volatile u8 res1[3];
volatile u8 UTXH;
volatile u8 res2[3];
volatile u8 URXH;
#else /* Little Endian */
volatile u8 UTXH;
volatile u8 res1[3];
volatile u8 URXH;
volatile u8 res2[3];
#endif
volatile u32 UBRDIV;
#ifdef __BIG_ENDIAN
volatile u8 res3[2];
volatile u16 UDIVSLOT;
#else
volatile u16 UDIVSLOT;
volatile u8 res3[2];
#endif
} s3c64xx_uart;
/* PWM TIMER (see manual chapter 10) */
typedef struct {
volatile u32 TCNTB;
volatile u32 TCMPB;
volatile u32 TCNTO;
} s3c64xx_timer;
typedef struct {
volatile u32 TCFG0;
volatile u32 TCFG1;
volatile u32 TCON;
s3c64xx_timer ch[4];
volatile u32 TCNTB4;
volatile u32 TCNTO4;
} s3c64xx_timers;
#endif /*__S3C64XX_H__*/

1
arch/arm/include/asm/emif.h
View file

@ -1165,7 +1165,6 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
extern u32 *const T_den;
extern u32 *const emif_sizes;
#endif
void config_data_eye_leveling_samples(u32 emif_base);

13
arch/arm/include/asm/mach-types.h
View file

@ -223,7 +223,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_MIOA701 1257
#define MACH_TYPE_ARMADILLO5X0 1260
#define MACH_TYPE_CC9P9360JS 1264
#define MACH_TYPE_SMDK6400 1270
#define MACH_TYPE_NOKIA_N800 1271
#define MACH_TYPE_EP80219 1281
#define MACH_TYPE_GORAMO_MLR 1292
@ -3640,18 +3639,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_cc9p9360js() (0)
#endif
#ifdef CONFIG_MACH_SMDK6400
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_arch_type __machine_arch_type
# else
# define machine_arch_type MACH_TYPE_SMDK6400
# endif
# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400)
#else
# define machine_is_smdk6400() (0)
#endif
#ifdef CONFIG_MACH_NOKIA_N800
# ifdef machine_arch_type
# undef machine_arch_type

87
arch/arm/include/asm/omap_gpmc.h Normal file
View file

@ -0,0 +1,87 @@
/*
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
* Rohit Choraria <rohitkc@ti.com>
*
* (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_OMAP_GPMC_H
#define __ASM_OMAP_GPMC_H
#include <asm/arch/omap_gpmc.h>
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define ECCCLEAR (0x1 << 8)
#define ECCRESULTREG1 (0x1 << 0)
#define ECCSIZE512BYTE 0xFF
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
#define ECCSIZE0SEL (0x000 << 0)
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
9, 10, 11, 12},\
.oobfree = {\
{.offset = 13,\
.length = 51 } } \
}
#endif
/* Large Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13},\
.oobfree = {\
{.offset = 14,\
.length = 50 } } \
}
#endif
/* Small Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {1, 2, 3},\
.oobfree = {\
{.offset = 4,\
.length = 12 } } \
}
#endif
/* Small Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {2, 3, 4},\
.oobfree = {\
{.offset = 5,\
.length = 11 } } \
}
#endif
#endif /* __ASM_OMAP_GPMC_H */

52
arch/arm/lib/crt0.S
View file

@ -24,6 +24,7 @@
#include <config.h>
#include <asm-offsets.h>
#include <linux/linkage.h>
/*
* This file handles the target-independent stages of the U-Boot
@ -63,46 +64,20 @@
* have some work left to do at this point regarding memory, so
* call c_runtime_cpu_setup.
*
* 6. Branch to either nand_boot() or board_init_r().
* 6. Branch to board_init_r().
*/
/*
* declare nand_boot() or board_init_r() to jump to at end of crt0
*/
#if defined(CONFIG_NAND_SPL)
.globl nand_boot
#elif ! defined(CONFIG_SPL_BUILD)
.globl board_init_r
#endif
/*
* start and end of BSS
*/
.globl __bss_start
.globl __bss_end
/*
* entry point of crt0 sequence
*/
.global _main
_main:
ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
#if defined(CONFIG_NAND_SPL)
/* deprecated, use instead CONFIG_SPL_BUILD */
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =(CONFIG_SPL_STACK)
#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
@ -118,8 +93,8 @@ _main:
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_sp, gd, addr_moni). Trick here is that
* we'll return 'here' but relocated.
* relocate_code(addr_moni). Trick here is that we'll return
* 'here' but relocated.
*/
ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */
@ -130,9 +105,7 @@ _main:
adr lr, here
ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */
add lr, lr, r0
ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */
mov r1, r8 /* r1 = gd */
ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */
ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
@ -153,21 +126,14 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
bl coloured_LED_init
bl red_led_on
#if defined(CONFIG_NAND_SPL)
/* call _nand_boot() */
ldr pc, =nand_boot
#else
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r8 /* gd_t */
ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */
/* call board_init_r */
ldr pc, =board_init_r /* this is auto-relocated! */
#endif
/* we should not return here. */
#endif
ENDPROC(_main)

17
board/actux1/u-boot.lds
View file

@ -61,6 +61,9 @@ SECTIONS
}
. = ALIGN (4);
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
@ -74,17 +77,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

17
board/actux2/u-boot.lds
View file

@ -61,6 +61,9 @@ SECTIONS
}
. = ALIGN (4);
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
@ -74,17 +77,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

17
board/actux3/u-boot.lds
View file

@ -61,6 +61,9 @@ SECTIONS
}
. = ALIGN (4);
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
@ -74,17 +77,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

4
board/ait/cam_enc_4xx/u-boot-spl.lds
View file

@ -25,7 +25,7 @@
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
arch/arm/cpu/arm926ejs/start.o (.text)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram

8
board/boundary/nitrogen6x/nitrogen6x.c
View file

@ -304,6 +304,9 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[1].max_bus_width = 4;
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
@ -328,11 +331,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
u32 get_board_rev(void)
{
return 0x63000;
}
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */

4
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
View file

@ -25,7 +25,7 @@
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
@ -38,7 +38,7 @@ SECTIONS
.text :
{
__start = .;
arch/arm/cpu/arm926ejs/start.o (.text)
arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram

9
board/davinci/da8xxevm/u-boot-spl-hawk.lds
View file

@ -34,15 +34,15 @@ SECTIONS
. = ALIGN(4);
.text :
{
arch/arm/cpu/arm926ejs/start.o (.text)
arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text)
drivers/mtd/nand/libnand.o (.text)
arch/arm/cpu/arm926ejs/start.o (.text*)
arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
drivers/mtd/nand/libnand.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
.rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
@ -58,6 +58,7 @@ SECTIONS
}
. = ALIGN(4);
__image_copy_end = .;
__rel_dyn_start = .;
__rel_dyn_end = .;
__dynsym_start = .;

17
board/dvlhost/u-boot.lds
View file

@ -61,6 +61,9 @@ SECTIONS
}
. = ALIGN (4);
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
@ -74,17 +77,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynstr*) }

32
board/freescale/mx31ads/u-boot.lds
View file

@ -37,23 +37,23 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/arm/cpu/arm1136/start.o (.text)
board/freescale/mx31ads/libmx31ads.o (.text)
arch/arm/lib/libarm.o (.text)
net/libnet.o (.text)
drivers/mtd/libmtd.o (.text)
arch/arm/cpu/arm1136/start.o (.text*)
board/freescale/mx31ads/libmx31ads.o (.text*)
arch/arm/lib/libarm.o (.text*)
net/libnet.o (.text*)
drivers/mtd/libmtd.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
common/env_embedded.o(.text*)
*(.text)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
.rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
*(.data)
*(.data*)
}
. = ALIGN(4);
@ -80,17 +80,23 @@ SECTIONS
_end = .;
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_start (OVERLAY) : {
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_end = .;
__bss_limit = .;
}
.bss_end __bss_end (OVERLAY) : {
KEEP(*(__bss_end));
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.bss*) }

3
board/freescale/mx31pdk/Makefile
View file

@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
ifdef CONFIG_SPL_BUILD
SOBJS := lowlevel_init.o
endif
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

5
board/freescale/mx31pdk/config.mk
View file

@ -1,5 +0,0 @@
ifdef CONFIG_NAND_SPL
CONFIG_SYS_TEXT_BASE = 0x87ec0000
else
CONFIG_SYS_TEXT_BASE = 0x87f00000
endif

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