Commit graph

62986 commits

Author SHA1 Message Date
Jagan Teki
b52a199e32 arm: rockchip: Add common cru.h
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.

So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.

The rest of rockchip cru files will add it in future.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
d49d8aa272 rockchip: rk3399: Enable DISPLAY_CPUINFO
RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
2952f39269 rockchip: Add cpu-info
Add cpu information for rockchip soc.

This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
1c37f60c28 rockpro-rk3399: Enable SPI Flash
Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
3d11196c80 roc-pc-rk3399: Enable SPI Flash
Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
c8b1684a8c rockchip: dts: Sync ROC-RK3399-PC changes from Linux
Sync the ROC-RK3399-PC device tree changes from Linux
with below commit details:

commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts:
rockchip: Enable MTD Flash on rk3399-roc-pc")

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
54b85a94e5 env: Enable SPI flash env for rockchip
Most of the SPI flash devices in rockchip are 16MiB size.

So, keeping U-Boot proper offset start from 128MiB with 1MiB
size and then start env of 8KiB would be a compatible location
between all variants of flash sizes.

This patch add env start from 0x14000 with a size of 8KiB.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
d7b433e40b env: kconfig: Restrict rockchip env for MMC
Rockchip do support SPI flash as well, so there is
a possibility of using flash environment for those
use cases.

So, restrict the current env offset, size for MMC.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
7c5f6d0aa4 rk3399: Check MMC env while defining it
rk3399 do support SPI flash as well, so there is
a possibility of using flash environment for those
usecases.

So define env device for MMC only when it is used
by specific configuration.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Thomas Hebb
95052b4b40 ram: rk3399: don't assume phy_io_config() uses real regs
In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.

However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.

This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):

Before:

  sdram_init() Starting SDRAM initialization...
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 0
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

After:

  sdram_init() Starting SDRAM initialization...
  sdram_init() sdram_init: data trained for rank 2, ch 0
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Tom Rini
e7ab1cb3f0 Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for 2020.04
- updates the Designware I2C driver
  - get timings from device tree
  - handle units in nanoseconds
  - make sure that the requested bus speed is not exceeded
  - few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field
2020-01-29 09:34:13 -05:00
Tom Rini
3e12744a90 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung
- Various exynos fixes
2020-01-28 21:10:32 -05:00
Tom Rini
b00c3c995b Prepare v2020.04-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-28 16:59:30 -05:00
Tom Rini
86e42b3629 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- spi cs accessing slaves (Bin Meng)
- spi prevent overriding established bus (Marcin Wojtas)
- support speed in spi command (Marek Vasut)
- add W25N01GV spinand (Robert Marko)
- move cadence_qspi to use spi-mem (Vignesh Raghavendra)
- add octal mode (Vignesh Raghavendra)
2020-01-27 19:57:13 -05:00
Marek Szyprowski
51521e4360 arm: exynos: odroid: Change autoboot script to use ${mmcbootdev}
This fixes the default boot command for the SD-card boot case.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-28 09:54:49 +09:00
Tom Rini
0ab16bf3b7 Merge branch '2020-01-27-master-imports'
- Add Dialog DA9063 PMIC support
- s35392a RTC bugfix
- Allow for opt-in of removal of DTB properties from the resulting
  binary.
2020-01-27 19:54:41 -05:00
Martin Fuzzey
b852cca8f0 pmic: allow dump command for non contiguous register maps
Some PMICs (such as the DA9063) have non-contiguous register maps.
Attempting to read the non implemented registers returns an error
rather than a dummy value which causes 'pmic dump' to terminate
prematurely.

Fix this by allowing the PMIC driver to return -ENODATA for such
registers, which will then be displayed as '--' by pmic dump.

Use a single error code rather than any error code so that
we can distinguish between a hardware failure reading the PMIC
and a non implemented register known to the driver.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2020-01-27 19:54:20 -05:00
Martin Fuzzey
7ae22d8479 power: regulator: add driver for Dialog DA9063 PMIC
Add a driver for the regulators in the the DA9063 PMIC.

Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Martin Fuzzey
483880c490 power: pmic: add driver for Dialog DA9063 PMIC
This adds the basic register access operations and child regulator
binding (if a regulator driver exists).

Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Ian Ray
e1d26a7642 rtc: s35392a: encode command correctly
The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Peng Ma
2d7818d04f cmd: sata: Add block unbind device function
If we didn't unbind the sata from block device, the same devices would
be added after sata remove,
This patch is to resolve this issue as below:

=> sata info
SATA#0:
	(3.0 Gbps)
SATA#1:
	(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
=> sata stop
=> sata info
SATA#0:
	(3.0 Gbps)
SATA#1:
	(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-27 19:54:20 -05:00
Anatolij Gustschin
d1b04cd3aa tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfig
This shrinks the image size: all -3840.0 text -3840.0

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Soeren Moch <smoch@web.de>
2020-01-27 19:54:20 -05:00
Anatolij Gustschin
43b6e38b27 dts: add property removal option CONFIG_OF_REMOVE_PROPS
This can be used for device tree size reduction similar as
CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the
built-in DTB unchanged to the kernel, thus we may not cut it
down unconditionally. Therefore enable the property removal
list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-01-27 19:54:20 -05:00
Marek Szyprowski
86c8871108 arm: exynos: Read default MMC device from XOM[7:5] pins
XOM pins provide information for iROM bootloader about the boot device.
Those pins are mapped to lower bits of OP_MODE register (0x10000008),
which is common for all Exynos SoC variants. Set the default MMC device id
to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for
the eMMC).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-28 09:54:05 +09:00
Vignesh Raghavendra
daa9405d7c spi: cadence-qspi: Add compatible for TI AM654
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
0f247848b6 spi: cadence-qspi: Add support for Cadence Octal SPI controller
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
658df8bd94 mtd: spi-nor-core: Add octal mode support
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
ffab212123 spi: cadence-qspi: Add direct mode support
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.

For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
d640772021 spi: cadence_qspi: Move to spi-mem framework
Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.

Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Robert Marko
370d33bc8c mtd: spinand: winbond: Add support for W25N01GV
Linux has supported W25N01GV for a long time, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
5502c88e67 spi: ti_qspi: Add support for CS other than CS0
Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0

Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Marcin Wojtas
f7dd537098 spi: prevent overriding established bus settings
The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.

The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.

This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Marek Vasut
6954756a15 cmd: spi: Permit setting bus frequency
The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions.
Allow changing that at runtime by specifying '@freq' bus frequency in Hz.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:21 +05:30
Bin Meng
bfcd9298b2 test: dm: spi: Fix sandbox dm_test_spi_find()
Per sandbox_cs_info(), sandbox spi controller only supports chip
select 0. Current test case tries to locate devices on chip select
1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs
number 1 should not return 0.

This updates the test case to handle it correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:21 +05:30
Bin Meng
7bacce524d dm: spi: Check cs number before accessing slaves
Add chip select number check in spi_find_chip_select().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27 22:27:21 +05:30
Michael Walle
383fded70c spi: nxp_fspi: new driver for the FlexSPI controller
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.

The port was straightforward:
 - remove the interrupt handling and the completion by busy polling the
   controller
 - remove locks
 - move the setup of the memory windows into claim_bus()
 - move the setup of the speed into set_speed()
 - port the device tree bindings from the original fspi_probe() to
   ofdata_to_platdata()

There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.

This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-27 22:27:21 +05:30
Tom Rini
051e03c0d7 Merge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Various clock fixes and enhancements
2020-01-27 07:19:26 -05:00
Simon Glass
2034f6c27f i2c: designware_i2c: Do more in the probe() method
Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:25:00 +01:00
Simon Glass
23ad52ebb1 i2c: designware_i2c: Separate out the speed calculation
We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.

Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:44 +01:00
Simon Glass
a8d2b515f9 i2c: designware_i2c: Move dw_i2c_speed_config to header
This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:29 +01:00
Simon Glass
d96440d1e3 i2c: designware_i2c: Add support for fast-plus speed
Fast-plus runs at 1MHz and is used by some devices. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:17 +01:00
Simon Glass
f3d461521a i2c: Update drivers to use enum for speed
Convert the obvious uses of i2c bus speeds to use the enum.

Use livetree access for code changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:24:02 +01:00
Simon Glass
b0a22d0fa9 i2c: stm32: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:42 +01:00
Simon Glass
4bef53684f i2c: omap: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:26 +01:00
Simon Glass
ab723b7781 i2c: kona_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:10 +01:00
Simon Glass
54290c666e i2c: designware_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:53 +01:00
Simon Glass
642400ced6 i2c: ast_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:41 +01:00
Simon Glass
7bd21b6264 i2c: Add enums for i2c speed and address size
Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.

Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.

Add these as well as an enum for the address mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:23 +01:00
Simon Glass
96fe11c3da i2c: designware_i2c: Add spike supression
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:01 +01:00
Simon Glass
e71b6f6622 i2c: designware_i2c: Rewrite timing calculation
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.

Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.

The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.

This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:21:51 +01:00