Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add cpu information for rockchip soc.
This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Enable winbond SPI flash for ROC-PC-RK3399 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable winbond SPI flash for ROC-PC-RK3399 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync the ROC-RK3399-PC device tree changes from Linux
with below commit details:
commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts:
rockchip: Enable MTD Flash on rk3399-roc-pc")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Most of the SPI flash devices in rockchip are 16MiB size.
So, keeping U-Boot proper offset start from 128MiB with 1MiB
size and then start env of 8KiB would be a compatible location
between all variants of flash sizes.
This patch add env start from 0x14000 with a size of 8KiB.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip do support SPI flash as well, so there is
a possibility of using flash environment for those
use cases.
So, restrict the current env offset, size for MMC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rk3399 do support SPI flash as well, so there is
a possibility of using flash environment for those
usecases.
So define env device for MMC only when it is used
by specific configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.
However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.
This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):
Before:
sdram_init() Starting SDRAM initialization...
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 0
phy_io_config() Invalid DRV value.
phy_io_config() Invalid DRV value.
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...
After:
sdram_init() Starting SDRAM initialization...
sdram_init() sdram_init: data trained for rank 2, ch 0
sdram_init() sdram_init: data trained for rank 2, ch 1
Channel 0: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR3, 933MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
sdram_init() Finish SDRAM initialization...
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
i2c changes for 2020.04
- updates the Designware I2C driver
- get timings from device tree
- handle units in nanoseconds
- make sure that the requested bus speed is not exceeded
- few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field
This fixes the default boot command for the SD-card boot case.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some PMICs (such as the DA9063) have non-contiguous register maps.
Attempting to read the non implemented registers returns an error
rather than a dummy value which causes 'pmic dump' to terminate
prematurely.
Fix this by allowing the PMIC driver to return -ENODATA for such
registers, which will then be displayed as '--' by pmic dump.
Use a single error code rather than any error code so that
we can distinguish between a hardware failure reading the PMIC
and a non implemented register known to the driver.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Add a driver for the regulators in the the DA9063 PMIC.
Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
This adds the basic register access operations and child regulator
binding (if a regulator driver exists).
Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
If we didn't unbind the sata from block device, the same devices would
be added after sata remove,
This patch is to resolve this issue as below:
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
=> sata stop
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
Type: Hard Disk
Supports 48-bit addressing
Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This can be used for device tree size reduction similar as
CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the
built-in DTB unchanged to the kernel, thus we may not cut it
down unconditionally. Therefore enable the property removal
list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
XOM pins provide information for iROM bootloader about the boot device.
Those pins are mapped to lower bits of OP_MODE register (0x10000008),
which is common for all Exynos SoC variants. Set the default MMC device id
to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for
the eMMC).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.
For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.
Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Linux has supported W25N01GV for a long time, so lets import it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0
Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.
The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.
This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions.
Allow changing that at runtime by specifying '@freq' bus frequency in Hz.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Per sandbox_cs_info(), sandbox spi controller only supports chip
select 0. Current test case tries to locate devices on chip select
1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs
number 1 should not return 0.
This updates the test case to handle it correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add chip select number check in spi_find_chip_select().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
controller
- remove locks
- move the setup of the memory windows into claim_bus()
- move the setup of the speed into set_speed()
- port the device tree bindings from the original fspi_probe() to
ofdata_to_platdata()
There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.
This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.
Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Convert the obvious uses of i2c bus speeds to use the enum.
Use livetree access for code changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this driver to use the new standard enums for speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.
Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.
Add these as well as an enum for the address mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.
Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.
The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.
This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
