I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Some boards need a higher DFSR value than the spec currently
recommends so give these boards the means to define there own.
For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
After issuing a STOP one must wait until the STOP has completed
on the bus before doing something new to the controller.
Also add an extra read of SR as the manual mentions doing that
is a good idea.
Remove surplus write of CR just before a write, isn't required and
could potentially disturb the I2C bus.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Headers should include headers containing prototypes and defines they
depend on, don't assume that they're included by somebody else.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.
Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is needed to correctly start the charging of an attached capacitor
or battery.
Signed-off-by: Werner Pfister <werner.pfister@intercontrol.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix warning: natsemi.c:757: warning: dereferencing type-punned pointer
will break strict-aliasing rules
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Ben Warren <biggerbadderben@gmail.com>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
After programming a new LAW, we should read-back the LAWAR register so that
we sync the writes. Otherwise, code that attempts to use the new LAW-mapped
memory might fail right away.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The value of I2C_TIMEOUT in fsl_i2c.c has several problems. First, it is
defined as CONFIG_HZ/4, but it is used as a count of microseconds, so it makes
no sense to derive it from a clock rate. Second, the current value (250) is
too low for some boards, so it needs to be increased. Third, the timeout
necessary for multiple-master arbitration is larger than the timeout for basic
read/write operations, so we shouldn't have a single constant for both timeouts.
Finally, it would be nice if we could override these values on a per-board
basis.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Tested-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Some files included my old standerd file header which had a "All
Rights Reserved" part. As this has never been my intention, I remove
these lines to make the files compatible with GPL v.2 and later.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
on 18th May 2008 as part of a general i386 / sc520 fixup which was never
applied
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Removed do_pinit() - now declared in cmd_pcmcia.c
Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other
PCMCIA drivers
signed/unsigned type fixups
Added semi-colon after default: label as required by newer gcc
The only board that appears to use this driver is the sc520_spunk which
is very old and very likely very broken anyway. I do not have one to test
whether this patch breaks anything functionaly, I have can only check
that it compiles without warning or error
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Cast first parameter to sata_cpy()
In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(),
ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in
include/libata.h which is included in ata.h which is included by all files
which include ata_piix.h (only ata_piix.c) so these definitions are
supurflous to (and conlict with) this in libata.h. Interestingly, my
compiler complains about ata_id_u64 already being defined, but not
ata_id_u32
ata_dump_id() is defined in include/libata.h and should not be static
(maybe should even use ata_dump_id() in libata.c
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller. This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers. For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok. However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.
We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access. Next we place PCICSRBAR
below the MMIO window. After which we try to setup the inbound windows
to map as much of memory as possible.
On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.
On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.
Additionally we changed all the CCSR register access to use proper IO
accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Change the code to use the PCIe capabilities register to determine if we
are a PCIe controller or not. Additionally cleaned up some white space
and formatting in the file.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
chips. This ECC mode is similar to NAND_ECC_HW, with the exception of
read_page API that first reads the OOB area, reads the data in chunks,
feeds the ECC from OOB area to the ECC hw engine and perform any
correction on the data as per the ECC status reported by the engine.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds a new "page" parameter to all NAND read_page/read_page_raw
APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the
page information to send the READOOB command and read the OOB area before
the data area.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch
WE would like this to become part of the u-boot GIT as well
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove unused read_spareram and add unlock_all as kernel does
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change %08lX to %08X in board.c. Remove unused variable
'oscillator' in mcf5227x/cpu_init.c and 'scm2' in
mcf532x/cpu_init.c. Provide argument type cast in
drivers/dma/MCD_dmaApi.c.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
see http://www.jedec.org/download/search/jep106Z.pdf
Add some second source legacy flash chips 256x8.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
if you don't have firmware installed for the PHY to come to life, this
wait can be painful - let's give the option to avoid it if we want.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Add a simple print for the Blackfin's Ethernet Rx function,
so we can debug incomming Ethernet functions easier.
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
- changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900
- changed CS8900_BASE to CONFIG_CS8900_BASE
- changed CS8900_BUS?? to CONFIG_CS8900_BUS??
- cleaned up line lengths
- modified VCMA9 command function that accesses the device
- removed MAC address initialization from lib_arm/board.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
.
.
byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This RTC is used in some Calao boards. The driver code is taken from
the linux rtc-m41t94 driver
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
In the process, also remove backward-compatiblity macros BIN_TO_BCD and
BCD_TO_BIN and update the sole board using them to use the new bin2bcd
and bcd2bin instead
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Previously, waiting for auto-negotiation would only occur if a valid
link had been detected. Problems arose when attempting to use a
tsec immediately after bootup but before link was achieved, eg:
=> dhcp
Auto-neg error, defaulting to 10BT/HD
eTSEC1: No link.
Auto-neg error, defaulting to 10BT/HD
eTSEC2: No link.
=>
With this patch applied the same operation as above resulted in:
=> dhcp
Waiting for PHY auto negotiation to complete. done
Enet starting in 1000BT/FD
Speed: 1000, full duplex
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
U-boot might use non-8-byte-aligned addresses for sending data, which
the kwgbe_send doesn't accept (bootp does this for me). This patch
copies the data to be sent to a malloced temporary buffer if it is
non-aligned.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch makes the device wait for up to 5 seconds for the link to
come up, similar to what many of the other network drivers do. This
avoids confusing situations where, e.g., a tftp fails when initiated
early after U-boot has started (before the link has come up).
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The Intel E1000 driver was making assumptions about the relationship between
some virtual, physical, and PCI addresses.
Also fix some bad usage of the DEBUGOUT macro
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Fix bug introduced by 9c048b5234.
The cfi_flash.c driver cast the flash buffer size to a uchar in
flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
uchar to enable buffer sizes to be larger.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fixed a misunderstanding in the original implementation, 'devnum' that
was used in the cpu/ppc4xx/4xx_enet.c implementation was NOT the
PHY's SMI address, rather it was the number of the MAC interface on
the CPU. The equivalent of this for uec_phy will be the UEC number
stored in mii_info->dev->name. Usage example is updated for uec.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
It is set to 0x1F by default and can be overwritten on the board
header file by defining CONFIG_UTBIPAR_INIT_TBIPA. This allows
the CPU to simply "reserve" one SMI address instead of using
a different one for each UEC.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
eth_setenv_enetaddr is avaible by upper layer
using this saves 204 bytes on total image size
used Local OUI instead of Marvell OUI for
random MAC address generation logic
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Fix E1000 build warning on AP1000 board
Fix the build warning on AP1000 board:
e1000.c:131: warning: 'e1000_read_eeprom' used but never defined
e1000.c:2012: warning: 'e1000_set_phy_mode' defined but not used
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
1. mv88E61xx driver compiler warnings fixed
2. idstr if-else statements changed to switch() construct
and added default case too.
This fixed idstr may be uninitialized warning
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds an FTMAC100 ethernet driver for Faraday A320 evaluation board.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
This chip is used in a number of boards manufactured by Calao-Systems
which should be supported soon. This driver provides the necessary
spi_read and spi_write functions necessary to communicate with the chip.
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards. As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.
IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Based on Intel PRO/1000 Network Driver 7.3.20-k2
Add Intel E1000 PCIE card support. The following cards are added:
INTEL_82571EB_COPPER
INTEL_82571EB_FIBER,
INTEL_82571EB_SERDES
INTEL_82571EB_QUAD_COPPER
INTEL_82571PT_QUAD_COPPER
INTEL_82571EB_QUAD_FIBER
INTEL_82571EB_QUAD_COPPER_LOWPROFILE
INTEL_82571EB_SERDES_DUAL
INTEL_82571EB_SERDES_QUAD
INTEL_82572EI_COPPER
INTEL_82572EI_FIBER
INTEL_82572EI_SERDES
INTEL_82572EI
INTEL_82573E
INTEL_82573E_IAMT
INTEL_82573L
INTEL_82546GB_QUAD_COPPER_KSP3
INTEL_80003ES2LAN_COPPER_DPT
INTEL_80003ES2LAN_SERDES_DPT
INTEL_80003ES2LAN_COPPER_SPT
INTEL_80003ES2LAN_SERDES_SPT
82571EB_COPPER dual ports,
82572EI single port,
82572EI_COPPER single port PCIE cards
and
82545EM_COPPER,
82541GI_LF
pci cards are tested on both P2020 board
and MPC8544DS board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Because twl4030 now has its own device files, move and rename
twl4030_mmc_config.
twl4030_mmc_config initializes the twl4030 power setting to
the mmc device. Because it is in the twl4030 power domain, move
it out of drivers/mmc/omap3_mmc.c and into drivers/power/twl4030.c.
The function was renamed to twl4030_power_mmc_init because all
the functions in this file are to have the format
twl4030_power_<device>_<action>
In this case the suffix is mmc_init so
device : mmc
action : init
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Heiko Schocher <hs@denx.de>
Because twl4030 now has its own device files, move exiting
omap3 power_init_r to a new location.
power_init_r is the only function in board/omap3/common.
It initializes the twl4030 power for the board and enables
the led.
The power part of the the function is moved to twl4030_power_init in
drivers/power/twl4030.c The power compilation is conditional on the
existing config variable CONFIG_TWL4030_POWER.
The led part is moved to twl4030_led_init in the new file
drivers/misc/twl4030_led.c The led compilation is conditional on
the new config variable CONFIG_TWL4030_LED
The directory board/omap3/common was removed because power_init_r
was the only function in it.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Heiko Schocher <hs@denx.de>
The Zoom2 power reset button is on the top right side of the
main board. Press and hold for about to 8 seconds to completely
reset the board.
Some of the beta boards have a hardware problem that prevents
using this feature. If is difficult to further characterize the
boards that fail. So disable resetting for all beta boards.
The Zoom1 reset button is the red circle on the top right,
front of the board. Press and hold the button for 8 seconds to
completely reset the board.
After analyzing beagle, it was determined that other boards
that use the twl4030 for power managment can also make use
this function.
The resetting is done by the power management part of the twl4030.
Since there is no existing drivers/power, add one.
The compilation of power/twl4030.h is controlled by the config
variable CONFIG_TWL4030_POWER
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Heiko Schocher <hs@denx.de>
This problem is seen on Zoom1 and Zoom2 in the startup and
when i2c probe is used
Before :
In: serial
Out: serial
Err: serial
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_pin: I2C_STAT=1000
I2C read: I/O error
timed out in wait_for_bb: I2C_STAT=1000
timed out in wait_for_bb: I2C_STAT=1000
Die ID #327c00020000000004013ddd05026013
Hit any key to stop autoboot: 0
OMAP3 Zoom1# i2c probe
Valid chip addresses:timed out in wait_for_bb: I2C_STAT=1000
02 03 04 05 06 07 08 09 0A 0B 0C 0D <snip>
After :
In: serial
Out: serial
Err: serial
Die ID #327c00020000000004013ddd05026013
Hit any key to stop autoboot: 0
OMAP3 Zoom1# i2c probe
Valid chip addresses: 48 49 4A 4B
The addresses are for the twl4030.
The prescalar that converts the function clock to the sampling
clock is hardcoded to 0. The reference manual recommends 7
if the function clock is 96MHz.
Instead of just changing the hardcoded values, the prescalar
is calculated from the value I2C_IP_CLK.
The i2c #defines are in kHz. The speed passed into the
i2c init routine is in Hz. To be consistent, change the
defines to be in Hz.
The timing calculations are based on what is done in the
linux 2.6.30 kernel in drivers/i2c/buses/i2c_omap.c as
apposed to what is done in TRM.
The major variables in the timing caculations are
specified as #defines that can be overriden as required.
The variables and their defaults are
I2C_IP_CLK SYSTEM_CLOCK_96
I2C_INTERNAL_SAMPLING_CLK 19200000
I2C_FASTSPEED_SCLL_TRIM 6
I2C_FASTSPEED_SCLH_TRIM 6
I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
I2C_HIGHSPEED_PHASE_TWO_SCLH I2C_FASTSPEED_SCLH_TRIM
This was runtime verified on Zoom1, Zoom2, Beagle and Overo.
The 400kHz and 3.4M cases were verifed on test Zoom1,
Zoom2, Beagle and Overo configurations.
Testing for omap2 will be done in a second step as Nishanth
and Jean-Christophe commented.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Heiko Schocher <hs@denx.de>
This patch adds support for the esd VME8349 board equipped with the
MPC8349. It's a VME PMC carrier board equipped with the Tundra
TSI148 VME-bridge.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch adds a new video driver
* adds common bus_vcxk framebuffer driver
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
[agust@denx.de: fixed lots of style issues before applying]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This change is cheked in Linux source and fix found to be in sync.
This patch is tested for USB host interface on Kirkwood based
Sheevaplug platform (ARM little endian board)
Risk: the impact of this patch is not validated on big endian board.
This need to be checked...
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The top build system sets up HOSTCFLAGS a bit and exports it, but other
places use HOST_CFLAGS instead. Unify the two as HOSTCFLAGS so that the
values stay in sync.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
ahci.c: In function 'ata_scsiop_read_capacity10':
ahci.c:616: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
biosemu.c: In function 'BE_setVGA':
biosemu.c:147: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes a compilation warning for some Ethernet PHY-less
PPC4xx platforms (440SPE based ones) and a potential compilation
error for 440SP platforms (use of undefined 'ethgroup' variable).
In the original code and in case of 440SPE platforms, 'ethgroup'
is initialized to -1 and never modified. Later in the function,
within an #ifdef statement, an 'if statement' executes code only
if 'ethgroup' is set to 4, therefore it is harmless to avoid
executing the 'if statement' by removing the CONFIG_440SPE from
the affected #ifdefs. In case of 440SP platforms with on-board
Ethernet PHY, 'ethgroup' is undefined but used (there are not such
platforms in the repository yet). All other architectures are not
affected by this change.
Signed-off-by: Alessio Centazzo acpatin@yahoo.com
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
With these fixes, this driver works properly for multi chip
addressging mode
Bugfixes:
1. Build error fixed for function mv88e61xx_busychk_multic-fixed
2. PHY dev address error detection- fixed
3. wrong busy bit was refered in function mv88e61xx_busychk -fixed
4. invalid data read ptr was refered for RD_PHY in case of
multichip addressing mode -fixed
The Multichip Address mode is tested with RD6281A board having
MV88E6165 switch on it
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The Marvell documentation for the 88f6281 states that the error coding
is only valid if the error summary and last frame bits in the transmit
descriptor status field are set. This patch adds checks for these for
transmit (I would get transmit errors on bootp with the current check,
which I believe are spurious).
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
kwgbe_send/recv both have loops waiting for the hardware to set a bit.
GCC 4.3.3 cleverly optimizes the send case to ... a while(1); loop. This
patch uses readl to force a read from device memory. Other volatile
accesses have also been replaced with readl/writel where appropriate
(as per suggestions on the U-boot mailing list).
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch sets the returned value to 0xFFFF if the PHY does not exist
and does not assert Transfer Acknowledge. A NULL check for the value
pointer is also added for buffer overflow protection.
Without this patch 'mii info' will show 'phantom' devices because the
value will be not be initialized and return with some random value.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
- changed CONFIG_DRIVER_SMC911X* to CONFIG_SMC911X*
- cleaned up line lengths
- modified all boards that override weak function in this driver
- added
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
These PHYs are on P2020RDB platform.
Also revamped Freescale copyright message in drivers/net/tsec.c.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
fix this gcc 4.4 warning:
tsec.c: In function 'tsec_init':
tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds the possibility to call a board specific
i2c bus reset routine for the fsl_i2c bus driver, and adds
this option for the keymile kmeter1 board.
The deblock sequence for this board is implemented and
tested in the following way:
CR = 0x20 (release SDA and SCL pin)
CR = 0xa0 (start read)
dummy read
dummy read
if 2. dummy read == 0x00
3. dummy read
CR = 0x80 (SDA and SCL now 1 SR = 0x86)
CR = 0x00 (Modul reset SR=0x81)
CR = 0x80 (SDA and SCL = 1, SR = 0x81)
Signed-off-by: Heiko Schocher <hs@denx.de>
Update fsl_sata to use common structures instead of casting
back and forth between the fsl specific ones and the common ones
(which are identical).
fsl_sata.c: In function 'scan_sata':
fsl_sata.c:550: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:549: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:548: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:545: note: initialized from here
fsl_sata.c:592: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:590: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:588: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:586: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
fsl_sata.c:579: warning: dereferencing pointer 'cfis' does break strict-aliasing rules
...
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to switch back to 1-bit before initialization or SD 2.0 cards
will fail to send SCR if we've switched to 4-bit already.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
This patch adds a SATA harddisk driver for the canyonlands.
This patch is kernel driver's porting.
This patch corresponded to not cmd_scsi but cmd_sata.
This patch divided an unused member with ifndef __U_BOOT__ in the structure.
[environment variable, boot script]
setenv bootargs root=/dev/sda7 rw
setenv bootargs ${bootargs} console=ttyS0,115200
ext2load sata 0:2 0x400000 /canyonlands/uImage
ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb
fdt addr 0x800000 0x4000
bootm 0x400000 - 0x800000
If you drive SATA-2 disk on Canyonlands, you must change parts from
PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using
following disks:
1.Vendor: Fujitsu Type: MHW2040BS
2.Vendor: Fujitsu Type: MHW2060BK
3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT
4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required)
5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required)
6.Vendor: Hitachi Type: HTS543232L9A300 (CONFIG_LBA48 required)
7.Vendor: Seagate Type: ST31000333AS (CONFIG_LBA48 required)
8.Vendor: Transcend Type: TS32GSSD25S-M
9.Vendor: MTRON Type: MSD-SATA1525-016
Signed-off-by: Kazuaki Ichinohe <kazuichi at fsi.co.jp>
So far the console API uses the following naming convention:
======Extract======
typedef struct device_t;
int device_register (device_t * dev);
int devices_init (void);
int device_deregister(char *devname);
struct list_head* device_get_list(void);
device_t* device_get_by_name(char* name);
device_t* device_clone(device_t *dev);
=======
which is too generic and confusing.
Instead of using device_XX and device_t we change this
into stdio_XX and stdio_dev
This will also allow to add later a generic device mechanism in order
to have support for multiple devices and driver instances.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Edited commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The curr_device variable really should be namespaced with a "sata_" prefix
since it is only used by the sata code. It also avoids random conflicts
with other pieces of code (like cmd_mmc):
common/libcommon.a(cmd_sata.o):(.data.curr_device+0x0):
multiple definition of `curr_device'
common/libcommon.a(cmd_mmc.o):(.data.curr_device+0x0): first defined here
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch adds support splash image positioning by adding an
additional variable "splashpos" to the environment. Please see
README for details.
Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Legacy NAND had been scheduled for removal. Any boards that use this
were already not building in the previous release due to an #error.
The disk on chip code in common/cmd_doc.c relies on legacy NAND,
and it has also been removed. There is newer disk on chip code
in drivers/mtd/nand; someone with access to hardware and sufficient
time and motivation can try to get that working, but for now disk
on chip is not supported.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Now that the 4xx NAND driver ndfc is moved to the common NAND driver
directory we don't need this #ifdef's anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch implements fdt_fixup_esdhc() function that is used to fixup
the device tree.
The function adds status = "disabled" propery if esdhc pins muxed away,
otherwise it fixups clock-frequency for esdhc nodes.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
a.k.a cfi_mtd.c does as cfi_flash.c does. This also prevents
the TQM834x build from doing a:
cfi_mtd.c:36: error: variably modified 'cfi_mtd_info' at file scope
cfi_mtd.c:37: error: variably modified 'cfi_mtd_names' at file scope
using gcc 4.4.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For JEDEC flash, we should issue word programming command relative to
base address rather than sector base address. Original source makes
SST Flash fails to program sectors which are not on the 0x10000 boundaries.
e.g.
SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
is 0x1000 bytes.
Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
it sends to 0x46555 and the chip fails to recognize that address.
This patch is tested with SST39LF040.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Stefan Roese <sr@denx.de>
AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.
The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.
Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
ehci-hcd.c: In function 'ehci_submit_root':
ehci-hcd.c:719: warning: value computed is not used
ehci-hcd.c:748: warning: value computed is not used
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
This patch fixes the access to the 'ehci' struct elements which should
have been taken care off in 4ef01010aa
Sorry about that.
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
These functions are no longer defined, so remove their prototypes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
This patch adds a NAND driver for the Marvell Kirkwood SoC's
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The bbt descriptors contains the pointer to the bbt pattern which
are statically initialized memory struct. When relocated to RAM,
these pointers will continue point to NOR flash(or L2 SRAM, or
other boot device). If the contents of NOR flash changed or L2
SRAM disabled, it'll hang the system.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The S3C2410 NAND driver source file is included in the makefile instead of
the object file.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Scott Wood <scottwood@freescale.com>
nand_util currently uses size_t which is arch dependent and not always a
unsigned long. Now use loff_t, as does the linux mtd layer.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped. Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
