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Merge branch 'master' of /home/wd/git/u-boot/custodians

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This commit is contained in:
Wolfgang Denk 2009-09-24 23:40:25 +02:00
commit 5e498dfab8
57 changed files with 1555 additions and 770 deletions
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4
MAKEALL
View file

@ -408,6 +408,10 @@ LIST_85xx=" \
PM856 \
sbc8540 \
sbc8548 \
sbc8548_PCI_33 \
sbc8548_PCI_66 \
sbc8548_PCI_33_PCIE \
sbc8548_PCI_66_PCIE \
sbc8560 \
socrates \
stxgp3 \

66
Makefile
View file

@ -2448,9 +2448,7 @@ ATUM8548_config: unconfig
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale
@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
MPC8540ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
@ -2516,41 +2514,17 @@ MPC8569MDS_config: unconfig
MPC8572DS_36BIT_config \
MPC8572DS_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
@$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
@$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale
P2020DS_36BIT_config \
P2020DS_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
@$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale
P1011RDB_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_P1011" >>$(obj)include/config.h ;
@$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
P1020RDB_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_P1020" >>$(obj)include/config.h ;
@$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
P2010RDB_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_P2010" >>$(obj)include/config.h ;
@$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
@$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
P1011RDB_config \
P1020RDB_config \
P2010RDB_config \
P2020RDB_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_P2020" >>$(obj)include/config.h ;
@$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
@ -2561,29 +2535,19 @@ PM856_config: unconfig
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
@$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560
sbc8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
sbc8548_config \
sbc8548_PCI_33_config \
sbc8548_PCI_66_config \
sbc8548_PCI_33_PCIE_config \
sbc8548_PCI_66_PCIE_config: unconfig
@$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
sbc8560_66_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
$(XECHO) "... 66 MHz PCI" ; \
else \
$(XECHO) "... 33 MHz PCI" ; \
fi
@$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
@$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560
socrates_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates

2
board/atum8548/law.c
View file

@ -49,7 +49,7 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),

6
board/freescale/mpc8536ds/law.c
View file

@ -31,11 +31,11 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),

2
board/freescale/mpc8540ads/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

6
board/freescale/mpc8544ds/law.c
View file

@ -30,10 +30,10 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
/* contains both PCIE3 MEM & IO space */
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),

2
board/freescale/mpc8560ads/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

6
board/freescale/mpc8572ds/law.c
View file

@ -29,11 +29,11 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),

224
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
struct fsl_pci_info pci_info[3];
u32 devdisr, pordevsr, io_sel, host_agent, temp32;
int first_free_busno = 0;
int num = 0;
int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
printf (" eTSEC1 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf (" eTSEC3 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
printf (" eTSEC4 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
struct pci_region *r = hose->regions;
u32 temp32;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
}
printf ("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCIE3 on bus %02x - %02x\n",
hose->first_busno,hose->last_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
* Device 1d has the first on-board memory BAR.
*/
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
temp32, 4, 0);
debug(" uli1572 read to %p\n", p);
in_be32(p);
}
} else {
printf (" PCIE3: disabled\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
* Device 1d has the first on-board memory BAR.
*/
pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
temp32, 4, 0);
debug(" uli1572 read to %p\n", p);
in_be32(p);
}
} else {
printf (" PCIE3: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
}
printf ("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCIE2 on bus %02x - %02x\n",
hose->first_busno,hose->last_busno);
} else {
printf (" PCIE2: disabled\n");
}
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
}
printf ("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf(" PCIE1 on bus %02x - %02x\n",
hose->first_busno,hose->last_busno);
} else {
printf (" PCIE1: disabled\n");
}
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif

14
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -387,19 +387,7 @@ void pci_init_board(void)
void
ft_board_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "ns16550",
"clock-frequency", bd->bi_busfreq, 1);
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);

29
board/freescale/p1_p2_rdb/ddr.c
View file

@ -23,10 +23,13 @@
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
@ -203,24 +206,40 @@ phys_size_t fixed_sdram (void)
{
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
size_t ddr_size;
struct cpu_type *cpu;
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
ddr_cfg_regs = &ddr_cfg_regs_400;
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
ddr_cfg_regs = &ddr_cfg_regs_533;
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
ddr_cfg_regs = &ddr_cfg_regs_667;
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
ddr_cfg_regs = &ddr_cfg_regs_800;
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
cpu = gd->cpu;
/* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs->cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
}
else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
return ddr_size;
}
phys_size_t initdram(int board_type)

4
board/freescale/p1_p2_rdb/law.c
View file

@ -26,9 +26,9 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),

42
board/freescale/p1_p2_rdb/pci.c
View file

@ -41,60 +41,62 @@ static struct pci_controller pcie2_hose;
void pci_init_board(void)
{
struct fsl_pci_info pci_info[2];
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
int num = 0;
struct fsl_pci_info pci_info[2];
u32 devdisr, pordevsr, io_sel, host_agent;
int first_free_busno = 0;
int num = 0;
int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
puts ("\n PCIE2 connected to Slot 1 as ");
printf ("%s (base address %lx)",
pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num],
SET_STD_PCIE_INFO(pci_info[num], 2);
printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
num++;
} else {
printf (" PCIE2: disabled\n");
}
puts("\n");
#else
set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE1
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
puts ("\n PCIE1 connected to Slot 2 as ");
printf ("%s (base address %lx)",
SET_STD_PCIE_INFO(pci_info[num], 1);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num],
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
num++;
} else {
printf (" PCIE1: disabled\n");
}
puts("\n");
#else
set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}

6
board/freescale/p2020ds/law.c
View file

@ -29,11 +29,11 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),

150
board/freescale/p2020ds/p2020ds.c
View file

@ -192,69 +192,42 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
int first_free_busno = 0;
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
struct fsl_pci_info pci_info[3];
u32 devdisr, pordevsr, io_sel, host_agent;
int first_free_busno = 0;
int num = 0;
volatile ccsr_fsl_pci_t *pci;
struct pci_controller *hose;
int pcie_ep, pcie_configured;
struct pci_region *r;
/* u32 temp32; */
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf(" eTSEC2 is in sgmii mode.\n");
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf(" eTSEC3 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE2
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
hose = &pcie2_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
printf("\n PCIE2 connected to ULI as %s (base addr %x)",
SET_STD_PCIE_INFO(pci_info[num], 2);
printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno = hose->last_busno+1;
printf(" PCIE2 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
@ -279,104 +252,47 @@ void pci_init_board(void)
} else {
printf(" PCIE2: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
hose = &pcie3_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
SET_STD_PCIE_INFO(pci_info[num], 3);
printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno = hose->last_busno+1;
printf(" PCIE3 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
hose = &pcie1_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
SET_STD_PCIE_INFO(pci_info[num], 1);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno = hose->last_busno+1;
printf(" PCIE1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif

2
board/pm854/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/pm856/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

4
board/sbc8548/Makefile
View file

@ -2,8 +2,8 @@
# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
# Added support for Wind River SBC8560 board
# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
# Added support for Wind River SBC8548 board
#
# See file CREDITS for list of people who contributed to this
# project.

12
board/sbc8548/law.c
View file

@ -32,8 +32,10 @@
*
* 0x0000_0000 0x0fff_ffff DDR 256M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
@ -48,8 +50,14 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
#ifdef CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
#endif
#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
#endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};

307
board/sbc8548/sbc8548.c
View file

@ -1,5 +1,6 @@
/*
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
*
* Copyright 2007 Embedded Specialties, Inc.
*
* Copyright 2004, 2007 Freescale Semiconductor.
@ -32,6 +33,8 @@
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
@ -49,25 +52,19 @@ int board_early_init_f (void)
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
(*rev) >> 4);
in_8(rev) >> 4);
/*
* Initialize local bus.
*/
local_bus_init ();
/*
* Hack TSEC 3 and 4 IO voltages.
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
ecm->eedr = 0xffffffff; /* clear ecm errors */
ecm->eeer = 0xffffffff; /* enable ecm errors */
out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
return 0;
}
@ -89,7 +86,7 @@ initdram(int board_type)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
out_be32(&gur->ddrdllcr, 0x81000000);
asm("sync;isync;msync");
udelay(200);
}
@ -126,24 +123,24 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
out_be32(&gur->lbiuiplldcr1, 0x00078080);
if (clkdiv == 16) {
gur->lbiuiplldcr0 = 0x7c0f1bf0;
out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
} else if (clkdiv == 8) {
gur->lbiuiplldcr0 = 0x6c0f1bf0;
out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
} else if (clkdiv == 4) {
gur->lbiuiplldcr0 = 0x5c0f1bf0;
out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
}
lbc->lcrr |= 0x00030000;
setbits_be32(&lbc->lcrr, 0x00030000);
asm("sync;isync;msync");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
}
/*
@ -152,7 +149,7 @@ local_bus_init(void)
void
sdram_init(void)
{
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@ -166,18 +163,24 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or3 = CONFIG_SYS_OR3_PRELIM;
out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
asm("msync");
lbc->br3 = CONFIG_SYS_BR3_PRELIM;
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
asm("msync");
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
asm("msync");
out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
asm("msync");
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
asm("msync");
/*
@ -189,7 +192,7 @@ sdram_init(void)
/*
* Issue PRECHARGE ALL command.
*/
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@ -199,7 +202,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@ -209,7 +212,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@ -218,7 +221,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@ -266,228 +269,132 @@ testdram(void)
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
#if !defined(CONFIG_SPD_EEPROM)
#define CONFIG_SYS_DDR_CONTROL 0xc300c000
/*************************************************************************
* fixed_sdram init -- doesn't use serial presence detect.
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/
long int fixed_sdram (void)
{
#define CONFIG_SYS_DDR_CONTROL 0xc300c000
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
ddr->cs0_bnds = 0x0000007f;
ddr->cs1_bnds = 0x008000ff;
ddr->cs2_bnds = 0x00000000;
ddr->cs3_bnds = 0x00000000;
ddr->cs0_config = 0x80010101;
ddr->cs1_config = 0x80010101;
ddr->cs2_config = 0x00000000;
ddr->cs3_config = 0x00000000;
ddr->timing_cfg_3 = 0x00000000;
ddr->timing_cfg_0 = 0x00220802;
ddr->timing_cfg_1 = 0x38377322;
ddr->timing_cfg_2 = 0x0fa044C7;
ddr->sdram_cfg = 0x4300C000;
ddr->sdram_cfg_2 = 0x24401000;
ddr->sdram_mode = 0x23C00542;
ddr->sdram_mode_2 = 0x00000000;
ddr->sdram_interval = 0x05080100;
ddr->sdram_md_cntl = 0x00000000;
ddr->sdram_data_init = 0x00000000;
ddr->sdram_clk_cntl = 0x03800000;
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
out_be32(&ddr->cs2_bnds, 0x00000000);
out_be32(&ddr->cs3_bnds, 0x00000000);
out_be32(&ddr->cs0_config, 0x80010101);
out_be32(&ddr->cs1_config, 0x80010101);
out_be32(&ddr->cs2_config, 0x00000000);
out_be32(&ddr->cs3_config, 0x00000000);
out_be32(&ddr->timing_cfg_3, 0x00000000);
out_be32(&ddr->timing_cfg_0, 0x00220802);
out_be32(&ddr->timing_cfg_1, 0x38377322);
out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
out_be32(&ddr->sdram_cfg, 0x4300C000);
out_be32(&ddr->sdram_cfg_2, 0x24401000);
out_be32(&ddr->sdram_mode, 0x23C00542);
out_be32(&ddr->sdram_mode_2, 0x00000000);
out_be32(&ddr->sdram_interval, 0x05080100);
out_be32(&ddr->sdram_md_cntl, 0x00000000);
out_be32(&ddr->sdram_data_init, 0x00000000);
out_be32(&ddr->sdram_clk_cntl, 0x03800000);
asm("sync;isync;msync");
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#endif
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
static struct pci_config_table pci_sbc8548_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
mpc85xx_config_via_usb, {0,0,0}},
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
mpc85xx_config_via_usb2, {0,0,0}},
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
mpc85xx_config_via_ac97, {0,0,0}},
{},
};
static struct pci_controller pci1_hose = {
config_table: pci_sbc8548_config_table};
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif /* CONFIG_PCI2 */
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
int first_free_busno=0;
#ifdef CONFIG_PCI
void
pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[2];
u32 devdisr, pordevsr, porpllsr, io_sel;
int first_free_busno = 0;
int num = 0;
#ifdef CONFIG_PCIE1
int pcie_configured;
#endif
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
porpllsr = in_be32(&gur->porpllsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
struct pci_region *r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
printf (" PCI host: %d bit, %s MHz, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
(pci_speed == 33000000) ? "33" :
(pci_speed == 66000000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter"
);
pci_arb ? "arbiter" : "external-arbiter");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
/* relocate config table pointers */
hose->config_table = \
(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
for (table = hose->config_table; table && table->vendor; table++)
table->config_device += gd->reloc_off;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
#ifdef CONFIG_PCIX_CHECK
if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
}
#endif
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCI2
{
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
if (pci_dual) {
printf (" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf (" PCI2: disabled\n");
}
}
#else
gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
#endif /* CONFIG_PCI2 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
struct pci_region *r = hose->regions;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE connected to slot as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
}
printf ("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
first_free_busno=hose->last_busno+1;
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf (" PCIE: disabled\n");
}
}
puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif
int board_eth_init(bd_t *bis)
{
tsec_standard_init(bis);
pci_eth_init(bis);
return 0; /* otherwise cpu_eth_init gets run */
}
int last_stage_init(void)

80
board/sbc8548/tlb.c
View file

@ -31,65 +31,73 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff800000 16M TLB for 8MB FLASH
* TLB 0: 64M Non-cacheable, guarded
* 0xfc000000 56M 8MB -> 64MB of user flash
* 0xff800000 8M boot FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
CONFIG_SYS_ALT_FLASH + 0x800000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Cacheable, non-guarded
* TLB 2: 256M Cacheable, non-guarded
* 0x0 256M DDR SDRAM
*/
#if !defined(CONFIG_SPD_EEPROM)
#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif
0, 2, BOOKE_PAGESZ_256M, 1),
#endif
/*
* TLB 4: 64M Non-cacheable, guarded
* TLB 3: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 16M PCI1 IO
* 0xe2000000 8M PCI1 IO
* 0xe2800000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
/*
* TLB 4: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
/*
* TLB 5: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM
* 0xf4000000 64M LBC SDRAM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
@ -103,6 +111,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
/*
* TLB 7: 4M Non-cacheable, guarded
* 0xfb800000 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
/*
* TLB 8: 4M Non-cacheable, guarded
* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

4
board/socrates/law.c
View file

@ -52,9 +52,9 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#if defined(CONFIG_SYS_FPGA_BASE)
SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/stx/stxgp3/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/stx/stxssa/law.c
View file

@ -54,7 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
/* Map the whole localbus, including flash and reset latch. */
SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/xes/xpedite5200/law.c
View file

@ -40,7 +40,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#if CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
#endif
#if CONFIG_SYS_PCI2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),

1
cpu/mpc85xx/Makefile
View file

@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o

49
cpu/mpc85xx/cpu.c
View file

@ -46,11 +46,20 @@ int checkcpu (void)
char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#endif
#else
#ifdef CONFIG_FSL_CORENET
u32 ddr_sync = 0;
#else
u32 ddr_ratio = 0;
#endif
#endif /* CONFIG_DDR_CLK_FREQ */
int i;
svr = get_svr();
@ -111,6 +120,19 @@ int checkcpu (void)
}
printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
#ifdef CONFIG_FSL_CORENET
if (ddr_sync == 1) {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
} else {
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
}
#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
@ -118,22 +140,26 @@ int checkcpu (void)
strmhz(buf2, sysinfo.freqDDRBus));
break;
case 0x7:
printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Synchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
default:
printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
printf(" DDR:%-4s MHz (%s MT/s data rate) "
"(Asynchronous), ",
strmhz(buf1, sysinfo.freqDDRBus/2),
strmhz(buf2, sysinfo.freqDDRBus));
break;
}
#endif
if (sysinfo.freqLocalBus > LCRR_CLKDIV)
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
else
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@ -143,6 +169,17 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i,
strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif
#ifdef CONFIG_SYS_DPAA_PME
printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
@ -184,7 +221,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
*/
unsigned long get_tbclk (void)
{
#ifdef CONFIG_FSL_CORENET
return (gd->bus_clk + 8) / 16;
#else
return (gd->bus_clk + 4UL)/8UL;
#endif
}

21
cpu/mpc85xx/cpu_init.c
View file

@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
* initialize a bunch of registers
*/
#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@ -229,6 +243,9 @@ void cpu_init_f (void)
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
corenet_tb_init();
#endif
}
@ -336,8 +353,8 @@ int cpu_init_r(void)
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
;
/* enable the cache */

68
cpu/mpc85xx/cpu_init_early.c
View file

@ -24,6 +24,51 @@
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
#ifdef CONFIG_FSL_CORENET
static void setup_ccsrbar(void)
{
u32 temp;
volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
volatile ccsr_local_t *ccm;
/*
* We can't call set_law() because we haven't moved
* CCSR yet.
*/
ccm = (void *)ccsr_virt;
out_be32(&ccm->law[0].lawbarh,
(u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
out_be32(&ccm->law[0].lawar,
LAW_EN | (0x1e << 20) | LAW_SIZE_4K);
in_be32((u32 *)(ccsr_virt + 0));
in_be32((u32 *)(ccsr_virt + 1));
isync();
ccm = (void *)CONFIG_SYS_CCSRBAR;
/* Now use the temporary LAW to move CCSR */
out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
out_be32(&ccm->ccsrar, CCSRAR_C);
temp = in_be32(&ccm->ccsrar);
disable_law(0);
}
#else
static void setup_ccsrbar(void)
{
u32 temp;
volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
temp = in_be32(ccsr_virt);
out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
}
#endif
#endif
/* We run cpu_init_early_f in AS = 1 */
void cpu_init_early_f(void)
{
@ -50,24 +95,15 @@ void cpu_init_early_f(void)
/* set up CCSR if we want it moved */
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
{
u32 temp;
volatile u32 *ccsr_virt =
(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
/* mas1 is the same as above */
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
/* mas1 is the same as above */
mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
write_tlb(mas0, mas1, mas2, mas3, mas7);
write_tlb(mas0, mas1, mas2, mas3, mas7);
temp = in_be32(ccsr_virt);
out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
}
setup_ccsrbar();
#endif
init_laws();

63
cpu/mpc85xx/cpu_init_nand.c Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
void cpu_init_f(void)
{
ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* LCRR - Clock Ratio Register - set up local bus timing
* when needed
*/
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
/* set MBECCDIS=1, SBECCDIS=1 */
out_be32(&l2cache->l2errdis,
(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
/* set L2E=1 & L2SRAM=001 */
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
/* Initialize L2 SRAM to zero */
l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
}

15
cpu/mpc85xx/fdt.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
* Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -27,6 +27,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <linux/ctype.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
@ -148,8 +149,14 @@ static inline void ft_fixup_l2cache(void *blob)
}
if (cpu) {
len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
cpu->name);
if (isdigit(cpu->name[0]))
len = sprintf(compat_buf,
"fsl,mpc%s-l2-cache-controller", cpu->name);
else
len = sprintf(compat_buf,
"fsl,%c%s-l2-cache-controller",
tolower(cpu->name[0]), cpu->name + 1);
sprintf(&compat_buf[len + 1], "cache");
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
@ -287,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 8, 1);
"timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);

68
cpu/mpc85xx/mp.c
View file

@ -26,6 +26,7 @@
#include <lmb.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
@ -135,7 +136,67 @@ ulong get_spin_addr(void)
return addr;
}
static void pq3_mp_up(unsigned long bootpg)
#ifdef CONFIG_FSL_CORENET
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
volatile ccsr_pic_t *pic;
int timeout = 10;
u32 nr_cpus;
struct law_entry e;
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
whoami = in_be32(&pic->whoami);
cpu_up_mask = 1 << whoami;
out_be32(&ccm->bstrl, bootpg);
e = find_law(bootpg);
out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
/* disable time base at the platform */
out_be32(&rcpm->ctbenrl, cpu_up_mask);
/* release the hounds */
up = ((1 << nr_cpus) - 1);
out_be32(&gur->brrl, up);
/* wait for everyone */
while (timeout) {
int i;
for (i = 0; i < nr_cpus; i++) {
if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
cpu_up_mask |= (1 << i);
};
if ((cpu_up_mask & up) == up)
break;
udelay(100);
timeout--;
}
if (timeout == 0)
printf("CPU up timeout. CPU up mask is %x should be %x\n",
cpu_up_mask, up);
/* enable time base at the platform */
out_be32(&rcpm->ctbenrl, 0);
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
}
#else
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_addr();
@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg)
devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
out_be32(&gur->devdisr, devdisr);
}
#endif
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
@ -217,7 +279,7 @@ void setup_mp(void)
if (i != -1) {
/* map reset page to bootpg so we can copy code there */
disable_tlb(i);
set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
@ -234,7 +296,7 @@ void setup_mp(void)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
pq3_mp_up(bootpg);
plat_mp_up(bootpg);
} else {
puts("WARNING: No reset page TLB. "
"Skipping secondary core setup\n");

3
cpu/mpc85xx/release.S
View file

@ -102,7 +102,8 @@ __secondary_start_page:
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync
lis r3,L2CSR0_L2FI@h
lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
mtspr SPRN_L2CSR0,r3
1:
mfspr r3,SPRN_L2CSR0

86
cpu/mpc85xx/speed.c
View file

@ -1,5 +1,6 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
[ 1] = 0, /* CC1 PPL / 2 */
[ 2] = 0, /* CC1 PPL / 4 */
[ 4] = 1, /* CC2 PPL / 1 */
[ 5] = 1, /* CC2 PPL / 2 */
[ 6] = 1, /* CC2 PPL / 4 */
[ 8] = 2, /* CC3 PPL / 1 */
[ 9] = 2, /* CC3 PPL / 2 */
[10] = 2, /* CC3 PPL / 4 */
[12] = 3, /* CC4 PPL / 1 */
[13] = 3, /* CC4 PPL / 2 */
[14] = 3, /* CC4 PPL / 4 */
};
const u8 core_cplx_PLL_div[16] = {
[ 0] = 1, /* CC1 PPL / 1 */
[ 1] = 2, /* CC1 PPL / 2 */
[ 2] = 4, /* CC1 PPL / 4 */
[ 4] = 1, /* CC2 PPL / 1 */
[ 5] = 2, /* CC2 PPL / 2 */
[ 6] = 4, /* CC2 PPL / 4 */
[ 8] = 1, /* CC3 PPL / 1 */
[ 9] = 2, /* CC3 PPL / 2 */
[10] = 4, /* CC3 PPL / 4 */
[12] = 1, /* CC4 PPL / 1 */
[13] = 2, /* CC4 PPL / 2 */
[14] = 4, /* CC4 PPL / 4 */
};
uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sysInfo->freqSystemBus = sysclk;
sysInfo->freqDDRBus = sysclk;
freqCC_PLL[0] = sysclk;
freqCC_PLL[1] = sysclk;
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
rcw_tmp = in_be32(&gur->rcwsr[3]);
for (i = 0; i < cpu_numcores(); i++) {
u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
sysInfo->freqProcessor[i] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
#define FM2_CLK_SEL 0x20000000
rcw_tmp = in_be32(&gur->rcwsr[7]);
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL)
sysInfo->freqPME = freqCC_PLL[2] / 2;
else
sysInfo->freqPME = sysInfo->freqSystemBus / 2;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL)
sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
else
sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL)
sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
else
sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
#endif
#endif
#else
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
#endif
#ifdef CONFIG_QE
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)

67
cpu/mpc85xx/u-boot-nand_spl.lds Normal file
View file

@ -0,0 +1,67 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de
*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
. = 0xfff00000;
.text : {
*(.text)
}
_etext = .;
.reloc : {
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
. = ALIGN(8);
.data : {
*(.rodata*)
*(.data*)
*(.sdata*)
}
_edata = .;
. = ALIGN(8);
__init_begin = .;
__init_end = .;
.resetvec ADDR(.text) + 0xffc : {
*(.resetvec)
} = 0xffff
__bss_start = .;
.bss : {
*(.sbss)
*(.bss)
}
_end = .;
}
ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");

4
cpu/mpc8xxx/cpu.c
View file

@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P4080, P4080_E, 8),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),

189
doc/README.sbc8548
View file

@ -1,27 +1,176 @@
Wind River SBC8548 reference board
===========================
Intro:
======
Copyright 2007, Embedded Specialties, Inc.
Copyright 2007 Wind River Systemes, Inc.
-----------------------------
The SBC8548 is a stand alone single board computer with a 1GHz
MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
ethernet connections.
1. Building U-Boot
------------------
The SBC8548 code is known to build using ELDK 4.1.
U-boot Configuration:
=====================
$ make sbc8548_config
Configuring for sbc8548 board...
The following possible u-boot configuration targets are available:
$ make
1) sbc8548_config
2) sbc8548_PCI_33_config
3) sbc8548_PCI_66_config
4) sbc8548_PCI_33_PCIE_config
5) sbc8548_PCI_66_PCIE_config
Generally speaking, most people should choose to use #5. Details
of each choice are listed below.
Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
will be left empty (M66EN high), and so the board will operate with
a base clock of 66MHz. Note that you need both PCI enabled in u-boot
and linux in order to have functional PCI under linux.
The second enables PCI support and builds for a 33MHz clock rate. Note
that if a 33MHz 32bit card is inserted in the slot, then the whole board
will clock down to a 33MHz base clock instead of the default 66MHz. This
will change the baud clocks and mess up your serial console output if you
were previously running at 66MHz. If you want to use a 33MHz PCI card,
then you should build a U-Boot with a _PCI_33_ config and store this
to flash prior to powering down the board and inserting the 33MHz PCI
card. [The above discussion assumes that the SW2[1-4] has not been changed
to reflect a different CCB:SYSCLK ratio]
The third option builds PCI support in, and leaves the clocking at the
default 66MHz. Options four and five are just repeats of option two
and three, but with PCI-e support enabled as well.
PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
a 33MHz PCI configuration is currently untested.)
=> pci 0
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1057 0x0012 Processor 0x20
00.01.00 0x8086 0x1026 Network controller 0x00
=> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
01.00.00 0x1957 0x0012 Processor 0x20
=> pci 2
Scanning PCI devices on bus 2
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
02.00.00 0x1148 0x9e00 Network controller 0x00
=>
2. Switch and Jumper Settings
-----------------------------
All Jumpers & Switches are in their default positions. Please refer to
the board documentation for details. Some settings control CPU voltages
and settings may change with board revisions.
Hardware Reference:
===================
3. Known limitations
--------------------
PCI:
The code to support PCI is currently disabled and has not been verified.
The following contains some summary information on hardware settings
that are relevant to u-boot, based on the board manual. For the
most up to date and complete details of the board, please request the
reference manual ERG-00327-001.pdf from www.windriver.com
Boot flash:
intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
Sodimm flash:
intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
Jumpers:
Jumper Name ON OFF
----------------------------------------------------------------
JP12 CS0/CS6 swap see note[*] see note[*]
JP13 SODIMM flash write OK writes disabled
write prot.
JP14 HRESET/TRST joined isolated
JP15 PWR ON when AC pwr use S1 for on/off
JP16 Demo LEDs lit not lit
JP19 PCI mode PCI PCI-X
[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
SODIMM flash and /CS6 is for the boot flash. Note that in this
alternate setting, you also need to switch SW2.8 to ON. Currently
u-boot doesn't support booting off the SODIMM in this alternate
setting without manually altering BR0/OR0 and BR6/OR6 in the
board config file appropriately.
Switches:
The defaults are marked with a *
Name Desc. ON OFF
------------------------------------------------------------------
S1 Pwr toggle n/a n/a
SW2.1 CFG_SYS_PLL0 1 0*
SW2.2 CFG_SYS_PLL1 1* 0
SW2.3 CFG_SYS_PLL2 1* 0
SW2.4 CFG_SYS_PLL3 1 0*
SW2.5 CFG_CORE_PLL0 1* 0
SW2.6 CFG_CORE_PLL1 1 0*
SW2.7 CFG_CORE_PLL2 1* 0
SW2.8 CFG_ROM_LOC1 1 0*
SW3.1 CFG_HOST_AGT0 1* 0
SW3.2 CFG_HOST_AGT1 1* 0
SW3.3 CFG_HOST_AGT2 1* 0
SW3.4 CFG_IO_PORTS0 1* 0
SW3.5 CFG_IO_PORTS0 1 0*
SW3.6 CFG_IO_PORTS0 1 0*
SerDes CLK(MHz) SW5.1 SW5.2
----------------------------------------------
25 0 0
100* 1 0
125 0 1
200 1 1
SerDes CLK spread SW5.3 SW5.4
----------------------------------------------
+/- 0.25% 0 0
-0.50% 1 0
-0.75% 0 1
No Spread* 1 1
SW4 settings are readable from the EPLD and are currently not used for
any hardware settings (i.e. user configuration switches).
LEDs:
Name Desc. ON OFF
------------------------------------------------------------------
D13 PCI/PCI-X PCI-X PCI
D14 3.3V PWR 3.3V no power
D15 SYSCLK 66MHz 33MHz
Default Memory Map:
start end CS<n> width Desc.
----------------------------------------------------------------------
0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
f800_0000 f8b0_1fff CS5 - EPLD
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
The EPLD on CS5 demuxes the following devices at the following offsets:
offset size width device
--------------------------------------------------------
0 1fff 8 7 segment display LED
10_0000 1fff 4 user switches
30_0000 1fff 4 HW Rev. register
b0_0000 1fff 8 8kB EEPROM

128
drivers/misc/fsl_law.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -29,7 +29,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define LAWAR_EN 0x80000000
/* number of LAWs in the hw implementation */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
@ -42,10 +41,62 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#elif defined(CONFIG_PPC_P4080)
#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
#endif
#ifdef CONFIG_FSL_CORENET
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
gd->used_laws |= (1 << idx);
out_be32(&ccm->law[idx].lawar, 0);
out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32));
out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff);
out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(&ccm->law[idx].lawar);
}
void disable_law(u8 idx)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
gd->used_laws &= ~(1 << idx);
out_be32(&ccm->law[idx].lawar, 0);
out_be32(&ccm->law[idx].lawbarh, 0);
out_be32(&ccm->law[idx].lawbarl, 0);
/* Read back so that we sync the writes */
in_be32(&ccm->law[idx].lawar);
return;
}
static int get_law_entry(u8 i, struct law_entry *e)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
u32 lawar;
lawar = in_be32(&ccm->law[i].lawar);
if (!(lawar & LAW_EN))
return 0;
e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) |
in_be32(&ccm->law[i].lawbarl);
e->size = lawar & 0x3f;
e->trgt_id = (lawar >> 20) & 0xff;
return 1;
}
#else
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
@ -56,12 +107,49 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
out_be32(lawar, 0);
out_be32(lawbar, addr >> 12);
out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(lawar);
}
void disable_law(u8 idx)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
gd->used_laws &= ~(1 << idx);
out_be32(lawar, 0);
out_be32(lawbar, 0);
/* Read back so that we sync the writes */
in_be32(lawar);
return;
}
static int get_law_entry(u8 i, struct law_entry *e)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * i;
volatile u32 *lawar = base + 8 * i + 2;
u32 temp;
temp = in_be32(lawar);
if (!(temp & LAW_EN))
return 0;
e->addr = (u64)in_be32(lawbar) << 12;
e->size = temp & 0x3f;
e->trgt_id = (temp >> 20) & 0xff;
return 1;
}
#endif
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx = ffz(gd->used_laws);
@ -94,18 +182,30 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
return idx;
}
void disable_law(u8 idx)
struct law_entry find_law(phys_addr_t addr)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
struct law_entry entry;
int i;
gd->used_laws &= ~(1 << idx);
entry.index = -1;
entry.addr = 0;
entry.size = 0;
entry.trgt_id = 0;
out_be32(lawar, 0);
out_be32(lawbar, 0);
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u64 upper;
return;
if (!get_law_entry(i, &entry))
continue;
upper = entry.addr + (2ull << entry.size);
if ((addr >= entry.addr) && (addr < upper)) {
entry.index = i;
break;
}
}
return entry;
}
void print_laws(void)
@ -173,7 +273,13 @@ void init_laws(void)
{
int i;
#if FSL_HW_NUM_LAWS < 32
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
#elif FSL_HW_NUM_LAWS == 32
gd->used_laws = 0;
#else
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)

2
drivers/pci/fsl_pci_init.c
View file

@ -450,7 +450,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
hose->first_busno, hose->last_busno);
return(hose->last_busno + 1);

6
include/asm-ppc/config.h
View file

@ -40,9 +40,11 @@
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
#else
#define CONFIG_MAX_CPUS 1
#define CONFIG_MAX_CPUS 1
#endif
#endif /* _ASM_CONFIG_H_ */

31
include/asm-ppc/fsl_law.h
View file

@ -1,8 +1,18 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
#define LAW_EN 0x80000000
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
@ -36,6 +46,25 @@ enum law_size {
LAW_SIZE_32G,
};
#ifdef CONFIG_FSL_CORENET
enum law_trgt_if {
LAW_TRGT_IF_PCIE_1 = 0x00,
LAW_TRGT_IF_PCIE_2 = 0x01,
LAW_TRGT_IF_PCIE_3 = 0x02,
LAW_TRGT_IF_RIO_1 = 0x08,
LAW_TRGT_IF_RIO_2 = 0x09,
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
LAW_TRGT_IF_DDR_INTRLV = 0x14,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
@ -64,6 +93,7 @@ enum law_trgt_if {
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
struct law_entry {
int index;
@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
extern struct law_entry find_law(phys_addr_t addr);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);

12
include/asm-ppc/fsl_lbc.h
View file

@ -311,9 +311,21 @@
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
defined(CONFIG_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
#elif defined(CONFIG_FSL_CORENET)
#define LCRR_CLKDIV_8 0x00000002
#define LCRR_CLKDIV_16 0x00000004
#define LCRR_CLKDIV_32 0x00000008
#else
#define LCRR_CLKDIV_4 0x00000002
#define LCRR_CLKDIV_8 0x00000004
#define LCRR_CLKDIV_16 0x00000008
#endif
/* LTEDR - Transfer Error Check Disable Register
*/

12
include/asm-ppc/fsl_pci.h
View file

@ -173,6 +173,18 @@ struct fsl_pci_info {
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCI##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
x.pci_num = num; \
}
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \

289
include/asm-ppc/immap_85xx.h
View file

@ -16,6 +16,29 @@
#include <asm/fsl_i2c.h>
#include <asm/fsl_lbc.h>
typedef struct ccsr_local {
u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */
u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */
u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */
#define CCSRAR_C 0x80000000 /* Commit */
u8 res1[4];
u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */
u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */
u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */
u8 res2[4];
u32 bstrh; /* 0x20 - Boot space translation register high */
u32 bstrl; /* 0x24 - Boot space translation register Low */
u32 bstrar; /* 0x28 - Boot space translation attributes register */
u8 res3[0xbd4];
struct {
u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */
u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */
u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */
u8 res4[4];
} law[32];
u8 res35[0x204];
} ccsr_local_t;
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
@ -165,7 +188,21 @@ typedef struct ccsr_ddr {
uint debug_2;
uint debug_3;
uint debug_4;
char res12[240];
uint debug_5;
uint debug_6;
uint debug_7;
uint debug_8;
uint debug_9;
uint debug_10;
uint debug_11;
uint debug_12;
uint debug_13; /* +0xF30 */
uint debug_14;
uint debug_15;
uint debug_16;
uint debug_17;
uint debug_18; /* +0xF44 */
char res12[184];
} ccsr_ddr_t;
/*
@ -1531,6 +1568,193 @@ typedef struct par_io {
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
#ifdef CONFIG_FSL_CORENET
typedef struct ccsr_gur {
u32 porsr1; /* 0xe0000 - POR status register */
u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */
u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */
u8 res2[12];
u32 gpiocr; /* 0xe0030 - GPIO control register */
u8 res3[12];
u32 gpoutdr; /* 0xe0040 - General-purpose output data register */
u8 res4[12];
u32 gpindr; /* 0xe0050 - General-purpose input data register */
u8 res5[12];
u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
u8 res6[12];
u32 devdisr; /* 0xe0070 - Device disable control */
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
#define FSL_CORENET_DEVDISR_RMU 0x08000000
#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
#define FSL_CORENET_DEVDISR_DMA1 0x00400000
#define FSL_CORENET_DEVDISR_DMA2 0x00200000
#define FSL_CORENET_DEVDISR_DDR1 0x00100000
#define FSL_CORENET_DEVDISR_DDR2 0x00080000
#define FSL_CORENET_DEVDISR_DBG 0x00010000
#define FSL_CORENET_DEVDISR_NAL 0x00008000
#define FSL_CORENET_DEVDISR_ELBC 0x00001000
#define FSL_CORENET_DEVDISR_USB1 0x00000800
#define FSL_CORENET_DEVDISR_USB2 0x00000400
#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
#define FSL_CORENET_DEVDISR_GPIO 0x00000080
#define FSL_CORENET_DEVDISR_ESPI 0x00000040
#define FSL_CORENET_DEVDISR_I2C1 0x00000020
#define FSL_CORENET_DEVDISR_I2C2 0x00000010
#define FSL_CORENET_DEVDISR_DUART1 0x00000002
#define FSL_CORENET_DEVDISR_DUART2 0x00000001
u8 res7[12];
u32 powmgtcsr; /* 0xe0080 - Power management status and control register */
u8 res8[12];
u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
u8 res9[8];
u32 pvr; /* 0xe00a0 - Processor version register */
u32 svr; /* 0xe00a4 - System version register */
u8 res10[8];
u32 rstcr; /* 0xe00b0 - Reset control register */
u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
u8 res11[8];
u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */
u8 res12[4]; /* Reserved: RSTRQMR2 */
u32 rstrqsr1; /* 0xe00c8 - Reset request status register */
u8 res13[4]; /* Reserved: RSTRQSR2 */
u8 res14[4]; /* Reserved: RSTRQWDTMRU */
u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
u8 res15[4]; /* Reserved: RSTRQWDTSRU */
u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
u32 brrl; /* 0xe00e4 Boot release register */
u8 res17[24];
u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/
u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */
u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/
u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/
u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */
u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/
u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/
u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/
u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/
u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/
u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/
u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/
u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/
u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/
u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
u8 res22[52]; /* Reserved: for future LIODN register expansion */
u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/
u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/
u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/
u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/
u8 res23[48]; /* Reserved: for future LIODN register expansion */
u8 res24[64]; /* Reserved */
u32 pblsr; /* 0xe0600 Preboot loader status register*/
u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/
u32 dmacr1; /* 0xe0608 DMA control register*/
u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/
u32 gensr1; /* 0xe0610 General status register*/
u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/
u32 gencr1; /* 0xe0620 General control register*/
u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/
u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */
u32 cgensrl; /* 0xe0634 Core general status register*/
u8 res29[8]; /* Reserved */
u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */
u32 cgencrl; /* 0xe0634 Core general control register*/
u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */
u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/
u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */
} ccsr_gur_t;
typedef struct ccsr_clk {
u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */
u8 res1[0x1c];
u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */
u8 res2[0x1c];
u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */
u8 res3[0x1c];
u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */
u8 res4[0x1c];
u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */
u8 res5[0x1c];
u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */
u8 res6[0x1c];
u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */
u8 res7[0x1c];
u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */
u8 res8[0x71c];
u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */
u8 res10[0x1c];
u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */
u8 res11[0x1c];
u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */
u8 res12[0x1c];
u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */
u8 res13[0x39c];
u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */
u8 res14[0x1c];
u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */
u8 res15[0x3dc];
} ccsr_clk_t;
typedef struct ccsr_rcpm {
u8 res1[4]; /* 0xe2000 - Reserved */
u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */
u8 res2[4]; /* 0xe2008 - Reserved */
u32 cdozcrl; /* 0xe200c - Core Doze Control Register */
u8 res3[4]; /* 0xe2010 - Reserved */
u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */
u8 res4[4]; /* 0xe2018 - Reserved */
u32 cnapcrl; /* 0xe201c - Core Nap Control Register */
u8 res5[4]; /* 0xe2020 - Reserved */
u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */
u8 res6[4]; /* 0xe2028 - Reserved */
u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */
u8 res7[4]; /* 0xe2030 - Reserved */
u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */
u8 res8[8]; /* Reserved */
u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */
u8 res9[12]; /* Reserved */
u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */
u8 res10[12]; /* Reserved */
u8 res11[4]; /* Reserved */
u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */
u8 res12[4]; /* Reserved */
u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */
u8 res13[4]; /* Reserved */
u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
u8 res14[4]; /* Reserved */
u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */
u8 res15[4]; /* Reserved */
u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */
u8 res16[4]; /* Reserved */
u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */
u8 res17[4]; /* Reserved */
u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */
u8 res18[0xf68];
} ccsr_rcpm_t;
#else
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
#ifdef CONFIG_MPC8536
@ -1542,6 +1766,8 @@ typedef struct ccsr_gur {
#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC85xx_PORBMSR_HA_SHIFT 16
@ -1645,42 +1871,65 @@ typedef struct ccsr_gur {
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#endif
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000
#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
#endif
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_USB_ADDR \

9
include/asm-ppc/mmu.h
View file

@ -504,13 +504,7 @@ extern int num_tlb_entries;
#endif
#endif
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
#define LAWAR_TRGT_IF 0x01F00000
#else
#define LAWBAR_BASE_ADDR 0x000FFFFF
#define LAWAR_TRGT_IF 0x00F00000
#endif
#ifdef CONFIG_MPC83xx
#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
@ -554,6 +548,7 @@ extern int num_tlb_entries;
#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#endif
#ifdef CONFIG_440
/* General */

4
include/asm-ppc/processor.h
View file

@ -1031,6 +1031,10 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
#define SVR_P4040 0x820100
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
#define SVR_P4080_E 0x820800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000

2
include/configs/MPC8536DS.h
View file

@ -27,7 +27,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_MPC8536DS_36BIT
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT 1
#endif

4
include/configs/MPC8572DS.h
View file

@ -27,6 +27,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */

13
include/configs/P1_P2_RDB.h
View file

@ -30,6 +30,19 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_MK_P1011RDB
#define CONFIG_P1011
#endif
#ifdef CONFIG_MK_P1020RDB
#define CONFIG_P1020
#endif
#ifdef CONFIG_MK_P2010RDB
#define CONFIG_P2010
#endif
#ifdef CONFIG_MK_P2020RDB
#define CONFIG_P2020
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */

4
include/configs/P2020DS.h
View file

@ -27,6 +27,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */

19
include/configs/SBC8540.h
View file

@ -24,22 +24,25 @@
* MA 02111-1307 USA
*/
/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
/*
* sbc8540 board configuration file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#if XXX
#define DEBUG /* General debug */
#define ET_DEBUG
/*
* Top level Makefile configuration choices
*/
#ifdef CONFIG_MK_66
#define CONFIG_PCI_66
#endif
#define TSEC_DEBUG
/* High Level Configuration Options */
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */

2
include/configs/XPEDITE5170.h
View file

@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3)
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
/*
* NAND flash configuration

2
include/configs/XPEDITE5200.h
View file

@ -103,7 +103,7 @@
* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration

2
include/configs/XPEDITE5370.h
View file

@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration

147
include/configs/sbc8548.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007 Wind River Systems <www.windriver.com>
* Copyright 2007,2009 Wind River Systems <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
* Copyright 2004, 2007 Freescale Semiconductor.
*
@ -24,26 +24,49 @@
/*
* sbc8548 board configuration file
*
* Please refer to doc/README.sbc85xx for more info.
*
* Please refer to doc/README.sbc8548 for more info.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
/*
* Top level Makefile configuration choices
*/
#ifdef CONFIG_MK_PCI
#define CONFIG_PCI
#define CONFIG_PCI1
#endif
#ifdef CONFIG_MK_66
#define CONFIG_SYS_CLK_DIV 1
#endif
#ifdef CONFIG_MK_33
#define CONFIG_SYS_CLK_DIV 2
#endif
#ifdef CONFIG_MK_PCIE
#define CONFIG_PCIE1
#endif
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
#undef CONFIG_PCI /* enable any pci type devices */
#undef CONFIG_PCI1 /* PCI controller 1 */
#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#undef CONFIG_PCI2
#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#ifdef CONFIG_PCI
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#ifdef CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@ -52,7 +75,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
/*
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
*/
#ifndef CONFIG_SYS_CLK_DIV
#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
#endif
#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
@ -164,6 +193,7 @@
*/
#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff800801
@ -172,9 +202,10 @@
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_ALT_FLASH}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
@ -196,13 +227,13 @@
#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
/*
* SDRAM on the Local Bus
* SDRAM on the Local Bus (CS3 and CS4)
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
* Base Register 3 and Option Register 3 configure SDRAM.
* Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR3, need:
@ -220,7 +251,7 @@
#define CONFIG_SYS_BR3_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR3, need:
* 64MB mask for AM, OR3[0:7] = 1111 1100
@ -235,6 +266,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
/*
* Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
* The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
*
* For BR4, need:
* Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
* port-size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
*
*/
#define CONFIG_SYS_BR4_PRELIM 0xf4001861
/*
* The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR4, need:
* 64MB mask for AM, OR3[0:7] = 1111 1100
* XAM, OR3[17:18] = 11
* 10 columns OR3[19-21] = 011
* 12 rows OR3[23-25] = 011
* EAD set for extra time OR[31] = 0
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
*/
#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@ -274,7 +339,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */
#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
@ -308,31 +373,27 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
#endif
#ifdef CONFIG_RIO
@ -343,14 +404,6 @@
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
@ -359,7 +412,7 @@
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */

17
include/configs/sbc8560.h
View file

@ -24,16 +24,23 @@
* MA 02111-1307 USA
*/
/* sbc8560 board configuration file */
/* please refer to doc/README.sbc8560 for more info */
/* make sure you change the MAC address and other network params first,
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
/*
* sbc8560 board configuration file.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
/*
* Top level Makefile configuration choices
*/
#ifdef CONFIG_MK_66
#define CONFIG_PCI_66
#endif
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */

6
include/e500.h
View file

@ -15,6 +15,12 @@ typedef struct
unsigned long freqDDRBus;
unsigned long freqLocalBus;
unsigned long freqQE;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freqPME;
#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */