Commit graph

51187 commits

Author SHA1 Message Date
Alexey Brodkin
a1b343d754 clean-up: Remove uselsess mentions of CONFIG_COMMAND_HISTORY
These were reminders that somehow slipped through the cracks
or were erroneously introduced after previous clean-ups.

Getting rid of then once again. Hopefully for good now :)

Where missing and appropriate replace with CONFIG_CMDLINE_EDITING
which really enables shell history as of now.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Jon Mason <jon.mason@broadcom.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:03 -04:00
Tom Rini
d2366dfe1d arm: Warn that starting with v2018.01 gcc-6 or later is required
There are more and more cases where if we do not use gcc-6.0 or later we
run into problems where our binaries are too large for the targets.
Given the prevalence of gcc-6.0 or later toolchains at this point in
time, we give notice now that starting with v2018.01 we will require
gcc-6 (or later) for ARM.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-27 16:49:02 -04:00
Simon Glass
43b41566f7 dm: sandbox: pwm: Add a basic pwm test
Unfortunately a test for the PWM uclass was not included when it was
submitted. This was noticed when trying to add more functionality:

   http://patchwork.ozlabs.org/patch/748172/

Add a simple test to get us started.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:02 -04:00
Lokesh Vutla
29f089a605 configs: keystone2: Standardise U-boot prompt
Standardise U-Boot prompt on all keystone2 platforms
instead of platform specific prompt.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27 16:48:59 -04:00
Adam Ford
44913aa52b OMAP3: Correct name of omap34xx_gpios when using DM_GPIO
The name of the gpio bank under DM_GPIO appear to be a copy-paste error.
This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27 08:13:48 -04:00
Adam Ford
71e48c26a6 omap3: i2c: correct register
The register names and offset were not correct as per the TRM for OMAP3530
and OMAP3630.  Correct the naing and offsets per the documentation

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2017-04-27 08:13:47 -04:00
Michal Simek
0a5559c10a arm64: zynqmp: Sync defconfig with Kconfig
Remove option which depends on MMC controller which is disabled for dc2.
Savedefconfig is removing it because of new dependencies.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-04-27 13:31:55 +02:00
Mike Looijmans
79ed06f2cc zynq-topic-miami.dts: Add usbotg0 alias to make USB actually work
Fixes the following problem:
zynq-uboot> run dfu_ram
Setting bus to 1
g_dnl_register: failed!, error: -19

The cause appears to be that the USB framework is looking for a usbotg aliases,
so add the alias to point to our USB device.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-04-27 13:31:55 +02:00
Tom Rini
6f008a2e16 Merge git://git.denx.de/u-boot-sunxi 2017-04-25 16:12:42 -04:00
Tom Rini
7f4ed7cb78 Merge git://git.denx.de/u-boot-fsl-qoriq 2017-04-25 16:11:35 -04:00
Tom Rini
9fde52a8d4 Merge branch 'master' of git://git.denx.de/u-boot-usb 2017-04-25 09:00:18 -04:00
Tom Rini
9ad99bee9c Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2017-04-25 08:59:56 -04:00
Alexey Brodkin
83cb46c286 ehci-ppc4xx: Prepare for usage of readl()/writel() accessors
We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.

Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
---------------->8---------------
  CC      drivers/usb/host/ehci-ppc4xx.o
drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
   ^
---------------->8---------------

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-25 12:50:13 +02:00
Heinrich Schuchardt
7f2e59aee5 usb: musb: avoid out of bound access in udc_setup_ep
For id = 15 an out of bound access occurs in udc_setup_ep().
Increase the size of epinfo[] from 30 to 32 to encompass
ids 0..15.

The problem was highlighted by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-04-25 12:50:12 +02:00
Heinrich Schuchardt
2511b2ed4d musb: properly detect failed initialization of controller
We want to check the result of musb_init_controller
and not the address were the result is stored.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-04-25 12:50:11 +02:00
Dalon Westergreen
6bd041f00d arm: socfpga: add cyclone5 based de10-nano board
Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-25 12:46:44 +02:00
Icenowy Zheng
e8f86a0261 sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I
Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other
chips the default value is 1 like other Allwinner SoCs.

Fix this default value.

The original wrong value has lead to wrong console on H3 Orange Pi
boards.

Fixes: 7095f86418 ("sunxi: Convert CONS_INDEX to Kconfig")

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-25 11:44:21 +02:00
Tom Rini
12af9399e7 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2017-04-24 21:08:42 -04:00
Tom Rini
9a1d64809d Merge branch 'master' of git://git.denx.de/u-boot-mips 2017-04-24 21:08:10 -04:00
York Sun
fedebf0d08 armv8: layerscape: Fix DDR size calcuation for SPL build
Commit 088454cd dropped return value from initram(), setting
gd->ram_size directly. Three boards were missed for SPL boot.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-24 09:07:12 -07:00
Yuantian Tang
026f30ec3e arm: psci: make psci usable on single core socs
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.

Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:07:12 -07:00
Sumit Garg
d14428c729 armv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND boot
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:06:26 -07:00
Sumit Garg
fa642559f5 armv8: fsl-layerscape: Add validation of PPA image from NAND and SD
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:05:20 -07:00
Sumit Garg
9fa3a54220 armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash
Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:03:30 -07:00
Hou Zhiqiang
2ac2e20ef8 armv8: ls1046aqds: Integrate FSL PPA
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:03:22 -07:00
Hou Zhiqiang
b6adbec0f9 armv8: ls1043aqds: enable FSL PPA
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:03:09 -07:00
Hou Zhiqiang
e1b0929059 armv8: ls1043aqds: Integrate FSL PPA
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:02:58 -07:00
Santan Kumar
99fe76d023 armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 09:02:46 -07:00
Alison Wang
5d267ec679 arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033
Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.

This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24 08:59:43 -07:00
Andreas Färber
2eff3b7179 sunxi: Fix arm64 fdtfile variable
Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing
the filename. However on arm64 that file is located in an allwinner
subdirectory.

To avoid the need for users/distros symlinking the .dtb files, prepend
the vendor directory for ARM64.

This aligns Pine64 with other boards such as Raspberry Pi 3.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-24 11:55:42 +05:30
Kyle Edwards
1967228b02 mips: qemu-mips/64: Expand malloc pool for CONFIG_SYS_BOOTPARAMS_LEN
Before this patch, CONFIG_SYS_BOOTPARAMS_LEN was the same size as
CONFIG_SYS_MALLOC_LEN. So, if malloc() had previously been called, and
initr_malloc_bootparams() was called, it would fail with an out-of-
memory error. This patch fixes this issue by expanding the malloc pool
to 256KB.

Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-04-21 13:54:47 +02:00
Kyle Edwards
9828d050cf mips: qemu-mips/64: Remove obsolete CONFIG_SYS_MONITOR_LEN from config
This fixes an issue with the saveenv command causing U-Boot to no
longer work on the QEMU Mips pseudoboard. Because the offset of the
environment was being determined by CONFIG_SYS_MONITOR_LEN, and this
value was less than the actual size of U-Boot, saveenv was overwriting
parts of the U-Boot code. Because CONFIG_SYS_MONITOR_LEN is no longer
used on MIPS, this patch removes it and places the environment at the
end of the pseudoboard's 4MB flash.

Signed-off-by: Kyle Edwards <kyleedwardsny@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-04-21 13:54:47 +02:00
Icenowy Zheng
f02abb0608 sunxi: add support for Lichee Pi Zero
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21 09:29:35 +02:00
Icenowy Zheng
e267d94011 sunxi: add DTSI file for V3s
As we have now V3s support in board code, the V3s DTSI file should also
be added.

Add also some CCU include headers to satisfy the DTSI file.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21 09:23:27 +02:00
Icenowy Zheng
c199489f17 sunxi: add basic V3s support
Basic U-Boot support is now present for V3s.

Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.

As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21 09:23:17 +02:00
Masahiro Yamada
4e7f8de426 ARM: dts: uniphier: sync Device Tree with Linux
- Use - instead of @ for OPP tables
 - Add input-delay properties to Cadence eMMC nodes
 - Restore full license text because code-diff is annoying
 - Fix NAND compatible strings

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20 23:50:02 +09:00
Masahiro Yamada
637548424b ARM: uniphier: show STM (SCP) status on boot and pinmon command
The SCP (System Control Processor) or what we call STM (Stand-by
MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20.
For these SoCs, show the information if STM is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20 23:49:56 +09:00
Masahiro Yamada
fed9c76641 ARM: uniphier: enable PSCI sysreset for uniphier_v8_defconfig
This configuration is supposed to be used with ARM Trusted Firmware,
so the SYSTEM_RESET is implemented in BL31.  Invoke PSCI instead of
U-Boot's own reset code because we need to coordinate with SCP
(System Control Processor) for the system-level power management.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20 23:49:50 +09:00
Masahiro Yamada
395e2142e4 ARM: uniphier: setup EHCI PHY paramters for LD11
Set the same PHY parameters as the Boot ROM uses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20 23:49:50 +09:00
Jernej Skrabec
1ae5def6be sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:37:31 +02:00
Jernej Skrabec
30ca20234e sunxi: video: Convert lcdc to use struct display_timing
Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.

It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:34:52 +02:00
Jernej Skrabec
5e023e7eb3 sunxi: video: Split out TCON code
TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:34:50 +02:00
Chen-Yu Tsai
10d8bc5a59 sunxi: Add support for Bananapi M2 Ultra
The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.

This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
0918648d82 sunxi: Add PSCI support for R40
The R40's CPU controls are a combination of sun6i and sun7i.

All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.

Last, the R40 does not have a secure SRAM block.

This patch adds a PSCI implementation for CPU bring-up and hotplug
for the R40.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
acef236454 sunxi: Fix CPUCFG address for R40
The R40 has the CPUCFG block at the same address as the A20.
Fix it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
50ae7ae583 sunxi: Enable SPL for R40
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
8201188cf9 sunxi: Use H3/A64 DRAM initialization code for R40
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
33559ffe5b gpio: sunxi: Add compatible string for R40 PIO
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
fab03e30e6 sunxi: Provide defaults for R40 DRAM settings
These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Chen-Yu Tsai
328ce7fd50 sunxi: Set PLL lock enable bits for R40
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.

This patch enables it for all the PLLs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00