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sunxi: video: Split out TCON code
TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Jernej Skrabec
Maxime Ripard
parent
10d8bc5a59
commit
5e023e7eb3
6 changed files with 362 additions and 285 deletions
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@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
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u32 output_color_coef[12]; /* 0x9d0 */
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};
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struct sunxi_lcdc_reg {
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u32 ctrl; /* 0x00 */
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u32 int0; /* 0x04 */
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u32 int1; /* 0x08 */
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u8 res0[0x04]; /* 0x0c */
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u32 tcon0_frm_ctrl; /* 0x10 */
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u32 tcon0_frm_seed[6]; /* 0x14 */
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u32 tcon0_frm_table[4]; /* 0x2c */
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u8 res1[4]; /* 0x3c */
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u32 tcon0_ctrl; /* 0x40 */
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u32 tcon0_dclk; /* 0x44 */
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u32 tcon0_timing_active; /* 0x48 */
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u32 tcon0_timing_h; /* 0x4c */
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u32 tcon0_timing_v; /* 0x50 */
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u32 tcon0_timing_sync; /* 0x54 */
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u32 tcon0_hv_intf; /* 0x58 */
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u8 res2[0x04]; /* 0x5c */
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u32 tcon0_cpu_intf; /* 0x60 */
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u32 tcon0_cpu_wr_dat; /* 0x64 */
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u32 tcon0_cpu_rd_dat0; /* 0x68 */
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u32 tcon0_cpu_rd_dat1; /* 0x6c */
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u32 tcon0_ttl_timing0; /* 0x70 */
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u32 tcon0_ttl_timing1; /* 0x74 */
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u32 tcon0_ttl_timing2; /* 0x78 */
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u32 tcon0_ttl_timing3; /* 0x7c */
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u32 tcon0_ttl_timing4; /* 0x80 */
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u32 tcon0_lvds_intf; /* 0x84 */
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u32 tcon0_io_polarity; /* 0x88 */
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u32 tcon0_io_tristate; /* 0x8c */
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u32 tcon1_ctrl; /* 0x90 */
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u32 tcon1_timing_source; /* 0x94 */
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u32 tcon1_timing_scale; /* 0x98 */
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u32 tcon1_timing_out; /* 0x9c */
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u32 tcon1_timing_h; /* 0xa0 */
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u32 tcon1_timing_v; /* 0xa4 */
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u32 tcon1_timing_sync; /* 0xa8 */
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u8 res3[0x44]; /* 0xac */
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u32 tcon1_io_polarity; /* 0xf0 */
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u32 tcon1_io_tristate; /* 0xf4 */
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u8 res4[0x108]; /* 0xf8 */
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u32 mux_ctrl; /* 0x200 */
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u8 res5[0x1c]; /* 0x204 */
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u32 lvds_ana0; /* 0x220 */
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u32 lvds_ana1; /* 0x224 */
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};
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struct sunxi_hdmi_reg {
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u32 version_id; /* 0x000 */
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u32 ctrl; /* 0x004 */
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@ -346,63 +300,6 @@ struct sunxi_tve_reg {
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#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
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#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1
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/*
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* LCDC register constants.
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*/
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#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
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#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
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#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
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#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
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#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
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#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
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#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
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#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
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#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
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#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
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#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
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#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
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#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
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#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
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#else
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
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#endif
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#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
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#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
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#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
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#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
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#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
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#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_LVDS_ANA0 0x40040320
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#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
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#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
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#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
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#else
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#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
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#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
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#endif
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#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
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#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
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/*
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* HDMI register constants.
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*/
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128
arch/arm/include/asm/arch-sunxi/lcdc.h
Normal file
128
arch/arm/include/asm/arch-sunxi/lcdc.h
Normal file
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@ -0,0 +1,128 @@
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/*
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* Sunxi platform timing controller register and constant defines
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _LCDC_H
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#define _LCDC_H
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struct ctfb_res_modes;
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struct sunxi_lcdc_reg {
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u32 ctrl; /* 0x00 */
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u32 int0; /* 0x04 */
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u32 int1; /* 0x08 */
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u8 res0[0x04]; /* 0x0c */
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u32 tcon0_frm_ctrl; /* 0x10 */
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u32 tcon0_frm_seed[6]; /* 0x14 */
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u32 tcon0_frm_table[4]; /* 0x2c */
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u8 res1[4]; /* 0x3c */
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u32 tcon0_ctrl; /* 0x40 */
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u32 tcon0_dclk; /* 0x44 */
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u32 tcon0_timing_active; /* 0x48 */
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u32 tcon0_timing_h; /* 0x4c */
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u32 tcon0_timing_v; /* 0x50 */
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u32 tcon0_timing_sync; /* 0x54 */
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u32 tcon0_hv_intf; /* 0x58 */
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u8 res2[0x04]; /* 0x5c */
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u32 tcon0_cpu_intf; /* 0x60 */
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u32 tcon0_cpu_wr_dat; /* 0x64 */
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u32 tcon0_cpu_rd_dat0; /* 0x68 */
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u32 tcon0_cpu_rd_dat1; /* 0x6c */
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u32 tcon0_ttl_timing0; /* 0x70 */
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u32 tcon0_ttl_timing1; /* 0x74 */
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u32 tcon0_ttl_timing2; /* 0x78 */
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u32 tcon0_ttl_timing3; /* 0x7c */
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u32 tcon0_ttl_timing4; /* 0x80 */
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u32 tcon0_lvds_intf; /* 0x84 */
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u32 tcon0_io_polarity; /* 0x88 */
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u32 tcon0_io_tristate; /* 0x8c */
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u32 tcon1_ctrl; /* 0x90 */
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u32 tcon1_timing_source; /* 0x94 */
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u32 tcon1_timing_scale; /* 0x98 */
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u32 tcon1_timing_out; /* 0x9c */
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u32 tcon1_timing_h; /* 0xa0 */
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u32 tcon1_timing_v; /* 0xa4 */
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u32 tcon1_timing_sync; /* 0xa8 */
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u8 res3[0x44]; /* 0xac */
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u32 tcon1_io_polarity; /* 0xf0 */
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u32 tcon1_io_tristate; /* 0xf4 */
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u8 res4[0x108]; /* 0xf8 */
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u32 mux_ctrl; /* 0x200 */
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u8 res5[0x1c]; /* 0x204 */
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u32 lvds_ana0; /* 0x220 */
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u32 lvds_ana1; /* 0x224 */
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};
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/*
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* LCDC register constants.
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*/
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#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
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#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
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#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
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#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
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#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
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#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
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#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
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#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
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#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
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#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
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#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
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#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
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#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
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#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
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#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
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#else
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#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
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#endif
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#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
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#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
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#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
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#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
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#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
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#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
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#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_LCDC_LVDS_ANA0 0x40040320
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#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
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#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
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#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
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#else
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#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
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#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
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#endif
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#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
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#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
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void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
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void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
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void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct ctfb_res_modes *mode,
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int clk_div, bool for_ext_vga_dac,
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int depth, int dclk_phase);
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void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct ctfb_res_modes *mode,
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bool ext_hvsync, bool is_composite);
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#endif /* _LCDC_H */
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@ -51,7 +51,6 @@ obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
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obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
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obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
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obj-$(CONFIG_VIDEO_SM501) += sm501.o
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
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obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
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obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
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obj-$(CONFIG_VIDEO_VESA) += vesa.o
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@ -64,3 +63,4 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
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obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
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obj-y += bridge/
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obj-y += sunxi/
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8
drivers/video/sunxi/Makefile
Normal file
8
drivers/video/sunxi/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# (C) Copyright 2000-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
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207
drivers/video/sunxi/lcdc.c
Normal file
207
drivers/video/sunxi/lcdc.c
Normal file
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@ -0,0 +1,207 @@
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/*
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* Timing controller driver for Allwinner SoCs.
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*
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* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/lcdc.h>
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#include <asm/io.h>
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#include "../videomodes.h"
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static int lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
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{
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int delay;
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delay = mode->lower_margin + mode->vsync_len +
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mode->upper_margin;
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if (mode->vmode == FB_VMODE_INTERLACED)
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delay /= 2;
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if (tcon == 1)
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delay -= 2;
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return (delay > 30) ? 30 : delay;
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}
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void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
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{
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/* Init lcdc */
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writel(0, &lcdc->ctrl); /* Disable tcon */
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writel(0, &lcdc->int0); /* Disable all interrupts */
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/* Disable tcon0 dot clock */
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clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
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/* Set all io lines to tristate */
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writel(0xffffffff, &lcdc->tcon0_io_tristate);
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writel(0xffffffff, &lcdc->tcon1_io_tristate);
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}
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void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
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{
|
||||
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
||||
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
|
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
|
||||
if (depth == 18)
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
|
||||
else
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
|
||||
#else
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
|
||||
udelay(1); /* delay at least 120 ns */
|
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
|
||||
const struct ctfb_res_modes *mode,
|
||||
int clk_div, bool for_ext_vga_dac,
|
||||
int depth, int dclk_phase)
|
||||
{
|
||||
int bp, clk_delay, total, val;
|
||||
|
||||
/* Use tcon0 */
|
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
|
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
|
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 0);
|
||||
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
|
||||
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
|
||||
|
||||
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
|
||||
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
|
||||
|
||||
writel(SUNXI_LCDC_X(mode->xres) |
|
||||
SUNXI_LCDC_Y(mode->yres), &lcdc->tcon0_timing_active);
|
||||
|
||||
bp = mode->hsync_len + mode->left_margin;
|
||||
total = mode->xres + mode->right_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
|
||||
|
||||
bp = mode->vsync_len + mode->upper_margin;
|
||||
total = mode->yres + mode->lower_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
|
||||
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len) |
|
||||
SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon0_timing_sync);
|
||||
|
||||
writel(0, &lcdc->tcon0_hv_intf);
|
||||
writel(0, &lcdc->tcon0_cpu_intf);
|
||||
#endif
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
||||
val = (depth == 18) ? 1 : 0;
|
||||
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
|
||||
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
|
||||
#endif
|
||||
|
||||
if (depth == 18 || depth == 16) {
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
|
||||
writel(((depth == 18) ?
|
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
|
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
|
||||
&lcdc->tcon0_frm_ctrl);
|
||||
}
|
||||
|
||||
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
|
||||
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
|
||||
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
|
||||
|
||||
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
||||
if (for_ext_vga_dac)
|
||||
val = 0;
|
||||
#endif
|
||||
writel(val, &lcdc->tcon0_io_polarity);
|
||||
|
||||
writel(0, &lcdc->tcon0_io_tristate);
|
||||
}
|
||||
|
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
|
||||
const struct ctfb_res_modes *mode,
|
||||
bool ext_hvsync, bool is_composite)
|
||||
{
|
||||
int bp, clk_delay, total, val, yres;
|
||||
|
||||
/* Use tcon1 */
|
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
|
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
|
||||
|
||||
clk_delay = lcdc_get_clk_delay(mode, 1);
|
||||
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
|
||||
((mode->vmode == FB_VMODE_INTERLACED) ?
|
||||
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
|
||||
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
|
||||
|
||||
yres = mode->yres;
|
||||
if (mode->vmode == FB_VMODE_INTERLACED)
|
||||
yres /= 2;
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_source);
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_scale);
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_out);
|
||||
|
||||
bp = mode->hsync_len + mode->left_margin;
|
||||
total = mode->xres + mode->right_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
|
||||
|
||||
bp = mode->vsync_len + mode->upper_margin;
|
||||
total = mode->yres + mode->lower_margin + bp;
|
||||
if (mode->vmode == FB_VMODE_NONINTERLACED)
|
||||
total *= 2;
|
||||
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
|
||||
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len) |
|
||||
SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon1_timing_sync);
|
||||
|
||||
if (ext_hvsync) {
|
||||
val = 0;
|
||||
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
|
||||
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
|
||||
writel(val, &lcdc->tcon1_io_polarity);
|
||||
|
||||
clrbits_le32(&lcdc->tcon1_io_tristate,
|
||||
SUNXI_LCDC_TCON_VSYNC_MASK |
|
||||
SUNXI_LCDC_TCON_HSYNC_MASK);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MACH_SUN5I
|
||||
if (is_composite)
|
||||
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
|
||||
SUNXI_LCDC_MUX_CTRL_SRC0(1));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/display.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/lcdc.h>
|
||||
#include <asm/arch/pwm.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/gpio.h>
|
||||
|
|
@ -23,10 +24,10 @@
|
|||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <video_fb.h>
|
||||
#include "videomodes.h"
|
||||
#include "anx9804.h"
|
||||
#include "hitachi_tx18d42vm_lcd.h"
|
||||
#include "ssd2828.h"
|
||||
#include "../videomodes.h"
|
||||
#include "../anx9804.h"
|
||||
#include "../hitachi_tx18d42vm_lcd.h"
|
||||
#include "../ssd2828.h"
|
||||
|
||||
#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
|
||||
#define PWM_ON 0
|
||||
|
|
@ -650,45 +651,7 @@ static void sunxi_lcdc_init(void)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/* Init lcdc */
|
||||
writel(0, &lcdc->ctrl); /* Disable tcon */
|
||||
writel(0, &lcdc->int0); /* Disable all interrupts */
|
||||
|
||||
/* Disable tcon0 dot clock */
|
||||
clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
|
||||
|
||||
/* Set all io lines to tristate */
|
||||
writel(0xffffffff, &lcdc->tcon0_io_tristate);
|
||||
writel(0xffffffff, &lcdc->tcon1_io_tristate);
|
||||
}
|
||||
|
||||
static void sunxi_lcdc_enable(void)
|
||||
{
|
||||
struct sunxi_lcdc_reg * const lcdc =
|
||||
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
||||
|
||||
setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
||||
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
|
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
|
||||
if (sunxi_display.depth == 18)
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
|
||||
else
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
|
||||
#else
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
|
||||
udelay(2); /* delay at least 1200 ns */
|
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
|
||||
udelay(1); /* delay at least 120 ns */
|
||||
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
|
||||
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
|
||||
#endif
|
||||
#endif
|
||||
lcdc_init(lcdc);
|
||||
}
|
||||
|
||||
static void sunxi_lcdc_panel_enable(void)
|
||||
|
|
@ -758,25 +721,12 @@ static void sunxi_lcdc_backlight_enable(void)
|
|||
gpio_direction_output(pin, PWM_ON);
|
||||
}
|
||||
|
||||
static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
|
||||
{
|
||||
int delay;
|
||||
|
||||
delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
|
||||
if (mode->vmode == FB_VMODE_INTERLACED)
|
||||
delay /= 2;
|
||||
if (tcon == 1)
|
||||
delay -= 2;
|
||||
|
||||
return (delay > 30) ? 30 : delay;
|
||||
}
|
||||
|
||||
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
|
||||
bool for_ext_vga_dac)
|
||||
{
|
||||
struct sunxi_lcdc_reg * const lcdc =
|
||||
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
||||
int bp, clk_delay, clk_div, clk_double, pin, total, val;
|
||||
int clk_div, clk_double, pin;
|
||||
|
||||
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
|
||||
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
|
||||
|
|
@ -796,73 +746,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
|
|||
|
||||
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
|
||||
|
||||
/* Use tcon0 */
|
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
|
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
|
||||
|
||||
clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
|
||||
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
|
||||
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
|
||||
|
||||
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
|
||||
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
|
||||
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
|
||||
&lcdc->tcon0_timing_active);
|
||||
|
||||
bp = mode->hsync_len + mode->left_margin;
|
||||
total = mode->xres + mode->right_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
|
||||
|
||||
bp = mode->vsync_len + mode->upper_margin;
|
||||
total = mode->yres + mode->lower_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
|
||||
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
|
||||
&lcdc->tcon0_timing_sync);
|
||||
|
||||
writel(0, &lcdc->tcon0_hv_intf);
|
||||
writel(0, &lcdc->tcon0_cpu_intf);
|
||||
#endif
|
||||
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
||||
val = (sunxi_display.depth == 18) ? 1 : 0;
|
||||
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
|
||||
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
|
||||
#endif
|
||||
|
||||
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
|
||||
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
|
||||
writel(((sunxi_display.depth == 18) ?
|
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
|
||||
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
|
||||
&lcdc->tcon0_frm_ctrl);
|
||||
}
|
||||
|
||||
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
|
||||
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
|
||||
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
|
||||
|
||||
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
||||
if (for_ext_vga_dac)
|
||||
val = 0;
|
||||
#endif
|
||||
writel(val, &lcdc->tcon0_io_polarity);
|
||||
|
||||
writel(0, &lcdc->tcon0_io_tristate);
|
||||
lcdc_tcon0_mode_set(lcdc, mode, clk_div, for_ext_vga_dac,
|
||||
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
|
||||
}
|
||||
|
||||
#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
|
||||
|
|
@ -872,65 +757,15 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
|
|||
{
|
||||
struct sunxi_lcdc_reg * const lcdc =
|
||||
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
||||
int bp, clk_delay, total, val, yres;
|
||||
|
||||
/* Use tcon1 */
|
||||
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
|
||||
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
|
||||
|
||||
clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
|
||||
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
|
||||
((mode->vmode == FB_VMODE_INTERLACED) ?
|
||||
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
|
||||
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
|
||||
|
||||
yres = mode->yres;
|
||||
if (mode->vmode == FB_VMODE_INTERLACED)
|
||||
yres /= 2;
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_source);
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_scale);
|
||||
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
|
||||
&lcdc->tcon1_timing_out);
|
||||
|
||||
bp = mode->hsync_len + mode->left_margin;
|
||||
total = mode->xres + mode->right_margin + bp;
|
||||
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
|
||||
|
||||
bp = mode->vsync_len + mode->upper_margin;
|
||||
total = mode->yres + mode->lower_margin + bp;
|
||||
if (mode->vmode == FB_VMODE_NONINTERLACED)
|
||||
total *= 2;
|
||||
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
|
||||
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
|
||||
|
||||
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
|
||||
&lcdc->tcon1_timing_sync);
|
||||
lcdc_tcon1_mode_set(lcdc, mode, use_portd_hvsync,
|
||||
sunxi_is_composite());
|
||||
|
||||
if (use_portd_hvsync) {
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
|
||||
|
||||
val = 0;
|
||||
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
||||
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
|
||||
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
||||
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
|
||||
writel(val, &lcdc->tcon1_io_polarity);
|
||||
|
||||
clrbits_le32(&lcdc->tcon1_io_tristate,
|
||||
SUNXI_LCDC_TCON_VSYNC_MASK |
|
||||
SUNXI_LCDC_TCON_HSYNC_MASK);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MACH_SUN5I
|
||||
if (sunxi_is_composite())
|
||||
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
|
||||
SUNXI_LCDC_MUX_CTRL_SRC0(1));
|
||||
#endif
|
||||
|
||||
sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
|
||||
|
|
@ -1212,6 +1047,8 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
|
|||
unsigned int address)
|
||||
{
|
||||
int __maybe_unused clk_div, clk_double;
|
||||
struct sunxi_lcdc_reg * const lcdc =
|
||||
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
||||
|
||||
switch (sunxi_display.monitor) {
|
||||
case sunxi_monitor_none:
|
||||
|
|
@ -1223,7 +1060,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
|
|||
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
|
||||
sunxi_hdmi_mode_set(mode, clk_div, clk_double);
|
||||
sunxi_composer_enable();
|
||||
sunxi_lcdc_enable();
|
||||
lcdc_enable(lcdc, sunxi_display.depth);
|
||||
sunxi_hdmi_enable();
|
||||
#endif
|
||||
break;
|
||||
|
|
@ -1253,7 +1090,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
|
|||
sunxi_composer_mode_set(mode, address);
|
||||
sunxi_lcdc_tcon0_mode_set(mode, false);
|
||||
sunxi_composer_enable();
|
||||
sunxi_lcdc_enable();
|
||||
lcdc_enable(lcdc, sunxi_display.depth);
|
||||
#ifdef CONFIG_VIDEO_LCD_SSD2828
|
||||
sunxi_ssd2828_init(mode);
|
||||
#endif
|
||||
|
|
@ -1265,13 +1102,13 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
|
|||
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
|
||||
sunxi_tvencoder_mode_set();
|
||||
sunxi_composer_enable();
|
||||
sunxi_lcdc_enable();
|
||||
lcdc_enable(lcdc, sunxi_display.depth);
|
||||
sunxi_tvencoder_enable();
|
||||
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
|
||||
sunxi_composer_mode_set(mode, address);
|
||||
sunxi_lcdc_tcon0_mode_set(mode, true);
|
||||
sunxi_composer_enable();
|
||||
sunxi_lcdc_enable();
|
||||
lcdc_enable(lcdc, sunxi_display.depth);
|
||||
sunxi_vga_external_dac_enable();
|
||||
#endif
|
||||
break;
|
||||
|
|
@ -1284,7 +1121,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
|
|||
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
|
||||
sunxi_tvencoder_mode_set();
|
||||
sunxi_composer_enable();
|
||||
sunxi_lcdc_enable();
|
||||
lcdc_enable(lcdc, sunxi_display.depth);
|
||||
sunxi_tvencoder_enable();
|
||||
#endif
|
||||
break;
|
||||
Loading…
Reference in a new issue