Commit graph

53468 commits

Author SHA1 Message Date
Tom Rini
5ef76e59c1 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-11-04 08:12:21 -05:00
Tom Rini
5d6fefa805 Merge tag 'mips-fixes-for-v2018.11' of git://git.denx.de/u-boot-mips
- replace the dynamic size of the relocation table
  with a fixed but configurable size
- fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol
2018-11-03 08:21:05 -04:00
Daniel Schwierzeck
9630146411 MIPS: make size of relocation table fixed but configurable
Currently the size of the relocation table will be shrunk
to the actual size needed. Although this gives a maximal
space saving, it messes up the _end symbol. This breaks
features like appended DTBs because the _end symbol doesn't
point to the real end of the U-Boot binary.

Remove the size shrinking and make the size of the relocation
table fixed but configurable. This follows the Linux approach
and the user can adjust the size to his needs.

Also rename the relocation table section from .rel to .data.reloc
to follow the Linux approach and to avoid ambiguities with the
.rel.* sections added by the linker.

Reported-by: Lars Povlsen <lars.povlsen@microsemi.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-02 22:39:07 +01:00
Marek Vasut
a376dde1de mmc: tmio: sdhi: Merge DTCNTL access into single register write
It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:07:04 +01:00
Marek Vasut
2fc10754d1 mmc: tmio: sdhi: Implement waiting for DAT0 line state
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.

This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00
Marek Vasut
dc1488f1d2 mmc: tmio: sdhi: Clear HS400 settings when resetting SCC
Make sure to clear HS400 configuration when resetting the SCC block.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:45 +01:00
Marek Vasut
52e1796883 mmc: tmio: sdhi: Touch SCC only when UHS capable
Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 16:04:44 +01:00
Marek Vasut
c83da2ebc0 mmc: tmio: Preinitialize regulator to 3.3V
Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
8171f99e7d mmc: tmio: Configure clock before any other IOS
Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
33633ebb1c mmc: tmio: Silence transfer errors when tuning
In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.

This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
b22c8d0de4 mmc: tmio: Improve error handling
Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
645a575aeb mmc: tmio: Simplify pinmux handling
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.

Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-02 15:57:14 +01:00
Marek Vasut
e5cb6bd9a2 ARM: rmobile: Generate fitting mem_map on Gen3
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.

This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec347638 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Marek Vasut
5dbdd3a600 pinctrl: renesas: Add POCCTRL handling to r8a77990
Add definition of the POCCTRL register and bits therein to R8A77990 E3
pincontrol driver. This allows the pincontrol driver to configure SDHI
pin voltage according to power-source DT property.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Marek Vasut
0ff9e4800f pinctrl: renesas: Fix DRV register offset
Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Tom Rini
99431c1c21 Merge tag 'arc-for-2018.11' of git://git.denx.de/u-boot-arc
Just 2 non-functinal changes:

 1. Rename of EMDK to EMSDP so it matches real marketing name
 2. Add essential README for IoTDK
2018-11-02 09:39:18 -04:00
Alexey Brodkin
a6b8c29fb8 iot_dk: Add README
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01 23:04:05 +03:00
Alexey Brodkin
adc9b09a23 emdk->emsdp: Rename board
Real marketing name of the board was recently updated so
to accommodate that change renaming the board and all
related to it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01 23:04:05 +03:00
Sam Protsenko
de8566a160 arm: ti: boot: Don't read environment partition
This part should've been remove in commit 88d60db011 ("arm: ti: boot:
Remove environment partition"), but I missed it somehow. Remove reading
dtb file from environment partition on eMMC, as we don't have it
anymore.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2018-11-01 10:02:43 -04:00
Jens Wiklander
c091dc7dad test: tee: fix resource leak in dm_test_tee()
Fixes possible resource leak in dm_test_tee() reported by Coverity.

Reported-by: Coverity (CID: 184175)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-11-01 10:02:43 -04:00
Patrick Delaunay
be6eb23931 cmd: remove CONFIG_SOURCE support in Makefile
This line is no more needed and can be removed.

Only CONFIG_CMD_SOURCE is defined in Kconfig and
used in defconfig files.

CONFIG_SOURCE if not defined in source code and
"config SOURCE" is not present in any Kconfig.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-01 10:02:43 -04:00
Lokesh Vutla
26da01f700 power: spl: add SPL_DM_REGULATOR_GPIO in Kconfig
The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig
does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-01 10:02:43 -04:00
Keerthy
1a25d9071b cmd: remoteproc: Fix the base of strtoul for ID conversion from 3 to 10
Currently the base is 3 fix it 10 so that IDs follow decimal system.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvulta@ti.com>
2018-11-01 10:02:43 -04:00
Andrei.Stefanescu@microchip.com
25ae865171 configs: sama5d2_ptc_ek: read environment from FAT
On our demo setup for SD card boot, the u-boot environment
is in a FAT partition.

This patch changes the default configuration, specifing that
the u-boot environment is in a FAT partition instead of raw MMC.

Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com>
Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-11-01 10:02:43 -04:00
Eugen.Hristev@microchip.com
6b4dba48ff configs: at91: at91sam9x5ek: fix bootcmd for NAND flash
The default bootcommand needs to be accurate w.r.t the nand memory map
at http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91sam9x5ekMainPage#NAND_Flash_demo_Memory_map

Updated to load kernel + dtb at right offsets and boot the zImage.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-11-01 10:02:10 -04:00
Martin Fuzzey
65b60897a7 w1: fix data abort if no one wire bus master present
When the "w1 bus" command is used with no bus master present
a data abort may occur.

This is because uclass_first_device() returns zero, but sets the output
struct udevice pointer to NULL in the no device found case.

Fix w1_get_bus() to account for this and return an error code
as is expected by the callers.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-11-01 10:02:10 -04:00
Martin Fuzzey
586d4b010e w1-eeprom: ds24xxx: fix data abort in ds24xxx_probe()
Data abort was occurring when using "w1 bus" with a DS24B33 present.

The abort occurred in the ds24xxx_probe() because the struct w1_device
pointer was NULL. This is because that structure  is allocated by
the parent device uclass (by .per_child_platdata_auto_alloc_size)
and thus the correct accessor is dev_get_parent_platdata() not
dev_get_platdata()

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-11-01 10:02:10 -04:00
Tom Rini
fdaccfeb5e Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-10-31 17:15:55 -04:00
Jun Nie
7bb0d212f2 sunxi: add support for Banana Pi M2 Zero board
Banana Pi M2 Zero is a board by Sinovoip with Allwinner H2+ SoC, 16-bit
512MiB DDR3 memory, a MicroSD slot, two MicroUSB ports (one OTG and one
powering-only) and a miniHDMI port.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
[jagan: Fixed board MAINTAINERS file]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-10-31 12:13:02 +05:30
Simon Goldschmidt
f48db4ede0 arm: socfpga: imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of
select ensures we can build without partition support (used to build
a network boot only version of SPL and U-Boot).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-31 01:41:10 +01:00
Stefan Roese
f457c52eb8 arm: socfpga: Fix bootcounter located at the end of internal SRAM
Commit 768f23dc8a ("ARM: socfpga: Put stack at the end of SRAM") broke
those socfpga boards that keep the bootcounter at the end of the
internal SRAM as the bootcounter needs 8 bytes by default and thus the
very first SPL call to board_init_f_alloc_reserve overwrites the
bootcounter.

This patch allows to move the initial stack pointer down a bit by
checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM
area and then using this address as location for the start of the
stack pointer.

No new macros / defines are added by this approach.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-31 01:41:10 +01:00
Simon Goldschmidt
d5de3d4978 arm: socfpga: fpga: fix type of local variable
The 'status' variable in 'socfpga_load()' for both gen5 and arria10
is of type 'unsigned long' while it is always used as 'int' only.
Change it to 'int'.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-31 01:41:10 +01:00
Tom Rini
a744370e6f Workaround and bug fix for Freescale PowerPC
Add workaround for Freescale USB erratum A005275.
 Correct RCW macros for T1080.
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Merge tag 'mpc85xx-for-v2018.11' of git://git.denx.de/u-boot-mpc85xx

Workaround and bug fix for Freescale PowerPC

Add workaround for Freescale USB erratum A005275.
Correct RCW macros for T1080.
2018-10-30 16:53:42 -04:00
Bin Meng
db148f2a69 powerpc: t1040: Correct RCW EC2 settings
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:19:43 -07:00
Bin Meng
c00d0012f5 powerpc: t1040: Correct RCW MAC2_GMII_SEL value
Per T1040RM (Rev. 1, 08/2015), the value of
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong
and should be 0x00000080 (bit 440 in the RCW).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:13:33 -07:00
Chris Packham
4eaf7f525a fsl/usb: Workaround for USB erratum-A005275
Workaround makes FS as default mode on all affected socs.

Add support to check erratum-A005275 validity for an soc. This info is
required to determine whether a given soc is affected by this erratum.
Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used
to enable workaround for the errata

Force FS mode as default by:
        - making EPS as FS
        - setting PFSC bit to disable HS chirping

This workaround can be disabled by mentioning "no_erratum_a005275" in
hwconfig string

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:13:05 -07:00
Tom Rini
454cf76184 Prepare v2018.11-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-29 16:04:26 -04:00
Tom Rini
2f07a9a6d1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-10-29 11:21:00 -04:00
Andre Przywara
5776610e9e sunxi: store DRAM size in SPL header
At the moment we rely on the infamous get_ram_size() function to learn
the actual DRAM size in U-Boot proper. This function has two issues:
1) It only works if the DRAM size is a power of two. We start to see
boards which have 3GB of (usable) DRAM, so this does not fit anymore.
2) As U-Boot has no notion of reserved memory so far, it will happily
ride through the DRAM, possibly stepping on secure-only memory. This
could be a region of DRAM reserved for OP-TEE or some other secure
payload, for instance. It will most likely crash in that case.

As the SPL DRAM init routine has very accurate knowledge of the actual
DRAM size, lets propagate this wisdom to U-Boot proper.
We re-purpose a currently reserved word in our SPL header for that.
The SPL itself stores the detected DRAM size there, and bumps the SPL
header version number in that case. U-Boot proper checks for a valid
SPL header and a high enough version number, then uses the DRAM size
from there. If the SPL header field is not sufficient, we fall back to
the old DRAM scanning routine.

Part of the DRAM might be present and probed by SPL, but not accessible
by the CPU. They're restricted in the main U-Boot binary, when accessing
the DRAM size from SPL header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
f8aa3f8d84 sunxi: add Kconfig option for the maximum accessible DRAM
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map
has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is
accessible.

Add a Kconfig option for the maximum accessible DRAM.

For A80 it should be a much higher value (8GiB), but as I have no A80
device to test and originally U-Boot only supports 2GiB DRAM on A80, it
currently still falls under the 2GiB situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
7009134c99 sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Andre Przywara
cff5c13849 sunxi: board.c: refactor SPL header checks
So far we have two users which want to look at the SPL header. We will
get more in the future.
Refactor the existing SPL header checks into a common function, to
simplify reusing the code.
Now that this is easy, add proper version checks to the DT name parsing.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Andre Przywara
55d481d201 sunxi: Extend SPL header versioning
On Allwinner SoCs we use some free bytes at the beginning of the SPL image
to store various information. We have a version byte to allow updates,
but changing this always requires all tools to be updated as well.

Introduce the concept of semantic versioning [1] to the SPL header:
The major part of the version number only changes on incompatible
updates, a minor number bump indicates backward compatibility.
This patch just documents the major/minor split, adds some comments
to the header file and uses the versioning information for the existing
users.

[1] https://semver.org

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
c6c2c85e4b sunxi: disable Pine A64 model detection code on other boards
The Pine A64 Plus/non-Plus model detection code is now built on all
64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in
use.

Disable them when the board is Pine A64 by adding a Kconfig option that
is only selected on Pine A64.

On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and
saves a 104 byte strstr() function, then makes SPL on H6 succeed to
build.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:07 +05:30
Tom Rini
d735d3b6cb Merge git://git.denx.de/u-boot-x86 2018-10-28 09:28:26 -04:00
Patrick Delaunay
22929e1266 drivers: cosmetic: Convert SPDX license tags to Linux Kernel style
Complete in the drivers directory the work started with
commit 83d290c56f ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-28 09:26:39 -04:00
Bin Meng
3d2be8003c x86: Fix car_uninit weak symbol definition
Since commit 80df194f01 ("x86: detect unsupported relocation types"),
an error message is seen on QEMU x86 target during boot:

do_elf_reloc_fixups32: unsupported relocation type 0x1 at fff841f0, offset = 0xfff00087
do_elf_reloc_fixups32: unsupported relocation type 0x2 at fff841f8, offset = 0xfff00091

Check offset 0xfff00087 and 0xfff00091 in the u-boot ELF image,

fff00087  000df401 R_386_32          00000000   car_uninit
fff00091  000df402 R_386_PC32        00000000   car_uninit

we see R_386_32 and R_386_PC32 relocation type is generated for
symbol car_uninit, which is declared as a weak symbol in start.S.

However the actual weak symbol implementation ends up nowhere. As
we can see below, it's *UND*.

$ objdump -t u-boot | grep car_uninit
00000000  w      *UND*  00000000 car_uninit

With this fix, it is normal now.

$ objdump -t u-boot | grep car_uninit
fff00094  w    F .text.start    00000001 car_uninit

Reported-by: Hannes Schmelzer <hannes@schmelzer.or.at>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2018-10-28 21:02:15 +08:00
Stefan Roese
87bb4fe869 x86: theadorable-x86-xxx_defconfig: Move VGA BIOS to make room for U-Boot
The build breaks because its not fitting the U-Boot binary into the ROM
image. So lets move VGA BIOS a bit to make room for the grown U-Boot
binary.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28 21:02:15 +08:00
Stefan Roese
6e1c943f3c x86: theadorable-x86: Generate and pass root=PARTUUID instead of /dev/sdaX
To enable the root device selection (kernel cmd-line) via PARTUUID, this
patch enables CMD_PART on all missing theadorable-x86 boards and
changes the default environment to generate the root=PARTUUID string
automatically.

This fixes problems that have been noticed on systems with multiple
SATA/AHCI controller connected via PCIe, where the device name for the
root device / partition (/dev/sdaX) was incorrect.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28 21:02:15 +08:00
Stefan Roese
0ca4405fcd x86: theadorable-x86-common: Change pci hotplug cmdline parameters (again)
This is needed for the PCIe hotplug to work correctly on some boards
with the newer Linux kernel versions.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28 21:02:15 +08:00