Commit graph

351 commits

Author SHA1 Message Date
Michal Simek
ebcc1a223e arm64: zynqmp: Wire mini-emmc1 configuration with zcu102
For testing purpose use zcu102 which has SD at controller 1 and this can
be used for testing this mini configuration.

U-Boot 2018.11-00279-gdc482e7ee092 (Nov 30 2018 - 10:22:56 +0100)

Model: ZynqMP MINI EMMC1
Board: Xilinx ZynqMP
DRAM:  512 MiB
EL Level:       EL3
MMC:   sdhci@ff170000: 0
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Michal Simek
f5ed777d29 arm64: zynqmp: Wire mini-emmc0 configuration with zcu100
For testing purpose use zcu100 which has SD at controller 0 and this can
be used for testing this mini configuration.

U-Boot 2018.11-00281-gc5d48466e76e (Nov 30 2018 - 10:41:05 +0100)

Model: ZynqMP MINI EMMC0
Board: Xilinx ZynqMP
DRAM:  512 MiB
EL Level:       EL3
MMC:   sdhci@ff160000: 0
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Michal Simek
e615f39e7f arm64: zynqmp: Start usb ethernet gadget automatically
If only usb ethernet gadget is enabled it can start automatically.
If more gagdets are enabled usb ethernet gadget can be bind by
"bind /amba/usb1@ff9e0000/dwc3@fe300000 usb_ether" (on zcu100)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Michal Simek
ee97a9996a arm64: zynqmp: Add mini mtest configuration
This configuration is useful when you want to run small u-boot and
perform DDR memory test to make sure that DDR is properly configured.
It is use for board bringup because alternative u-boot memory tests is
quite good.
Configuration is running out of OCM.

As is done for others mini configurations 0x80 bytes for variables is
enough and only default variables are stored there.

Alternative memtest is enabled and also 2GB of DDR via DTS files.
Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init()
from zcu102 for testing purpose.
In case of size issue this can be moved to SPL configuration as is done
for mini_qspi configuration but it is not a problem now.

Log:
U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100)

Model: ZynqMP MINI
Board: Xilinx ZynqMP
DRAM:  WARNING: Initializing TCM overwrites TCM content
2 GiB
EL Level:       EL3
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Michal Simek
a837cfe5b2 arm64: zynqmp: Enable SPL for mini qspi configuration
Wire up mini_qspi SPL with zcu102 for testing purpose.
Normally mini u-boot runs with FSBL/SPL for certain board.
Enabling SPL and configuration from zcu102 helps with testing.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 15:13:57 +01:00
Michal Simek
fdba86972f ARM: zynq: Wire SPL configuration for cse nor/nand targets
These symlinks are here only for testing purpose where SPL is used
for soc configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:31:02 +01:00
Michal Simek
656185a5d7 microblaze: Use standard functions for memory decoding
The standard function is less error prone than custom one.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:55 +01:00
Michal Simek
0dc69f4193 ARM: zynq: Guard zynq_help_text with CONFIG_SYS_LONGHELP
If SYS_LONGHELP is disabled the following warning is generated:
board/xilinx/zynq/cmds.c:496:13: warning: ‘zynq_help_text’ defined but
not used [-Wunused-variable]

Normal way for fixing this is to guard the whole variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:54 +01:00
Siva Durga Prasad Paladugu
5473f245d0 arm64: zynqmp: Fix logic in CG/EG/EV detection
The VCU disable bit(8) in IP disable register of efuse
is valid only if PL powered up and hence PL powerup status
has to be considered while determining the CG part also.
This patch considers the PL powerup status and ignores the VCU
disable bit if PL not powered up.
This fixes the issue of "unknown" id for CG parts if PL not powered up
and VCU bit(8) is not set.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:54 +01:00
Siva Durga Prasad Paladugu
5860bc16b9 arm64: zynqmp: Add new command for TCM initialization
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00
Michal Simek
6bfe3fffac arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 14:58:45 +02:00
Siva Durga Prasad Paladugu
b94a8271cc arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Tom Rini
b1aad8dbe2 zynqmp: Add avnet_ultra96_rev1_defconfig to the lits of boards
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-07 11:36:39 -04:00
Michal Simek
2570e12960 arm64: zynqmp: Add support for Avnet Ultra96
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files
and point to origin internal board name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Luis Araneda
58f449676a arm: zynq: add support for the zybo z7 board
The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
8a32077ea6 microblaze: Add missing quotes around XILINX_MICROBLAZE0_HW_VER
This issue is reported by kconfiglib:
warning: style: quotes recommended around default value for string
symbol XILINX_MICROBLAZE0_HW_VER (defined at
board/xilinx/microblaze-generic/Kconfig:37)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Siva Durga Prasad Paladugu
12308b128f lib: fdtdec: Rename routine fdtdec_setup_memory_size()
This patch renames the routine fdtdec_setup_memory_size()
to fdtdec_setup_mem_size_base() as it now fills the
mem base as well along with size.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-19 10:49:56 +02:00
Vipul Kumar
0358cee595 arm64: zynqmp: Added support of mmio read and write commands
This patch added support of mmio read and write commands. These commands
can be used to read and write registers from the u-boot command line.
It can be useful in debugging.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:56 +02:00
Michal Simek
4a69366967 microblaze: Convert generic platform to DM gpio
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.

GPIO reset is handled via sysreset with adding this fragment to DT.

gpio-restart {
	compatible = "gpio-restart";
	gpios = <&reset_gpio 0 0 0>;
	/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};

hard-reset-gpio property is not documented and also handled.
Conversion is required.

Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Shreenidhi Shedi
6ec6f5841d microblaze: Support for watchdog_reset in init
We should support watchdog reset so that WATCHDOG_RESET will function
properly.

Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Shreenidhi Shedi
88811bb5a1 microblaze: Delete Xilinx watchdog related macros
These macros are not required anymore. These will be taken from
configuration file.

Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Shreenidhi Shedi
35912528a8 microblaze: Cosmetic changes in Microblaze related files
Signed-off-by: Shreenidhi Shedi <yesshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Vipul Kumar
8c258e6245 arm64: zynqmp: Changed zynqmp command to handle subcommands with U_BOOT_CMD_MKENT
This patch changed zynqmp command to handle subcommands with
U_BOOT_CMD_MKENT.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Michal Simek
501fc50a29 arm: zynq: Try to enable the first watchdog via aliases
The same change as was done for zynqmp with this description:

Add support for enabling the first watchdog pointed via aliases.

DT fragment:
	aliases {
		...
		watchdog0= &watchdog0;
		watchdog1 = &watchdog_lpd;
		...
	};

<zynqmp example removed>

Till this patch the first watchdog found in DT was used and started
which is not enabling all possible configuration based on user request.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Michal Simek
1fbca0db5d arm64: zynqmp: Try to enable the first watchdog via aliases
Add support for enabling the first watchdog pointed via aliases.

DT fragment:
	aliases {
		...
		watchdog0 = &watchdog0;
		watchdog1 = &watchdog_lpd;
		...
	};

dm tree fragment for above configuration with patch applied:
ZynqMP> dm tree
 Class    index  Probed  Driver      Name
-----------------------------------------
...
 watchdog    0  [   ]   cdns_wdt    |   |-- watchdog@ff150000
 watchdog    1  [ + ]   cdns_wdt    |   `-- watchdog@fd4d0000
...

dm uclass fragment:
ZynqMP> dm uclass
...
uclass 75: watchdog
0   watchdog@ff150000 @ 7df02f40, seq -1, (req 1)
1 * watchdog@fd4d0000 @ 7df02ff0, seq 0, (req 0)
...

It is visible that index 1 is IP with seq 0 which means that FPD
watchdog (@fd4d0000) is in DT below LPD watchdog (@ff150000).

Till this patch the first watchdog found in DT was used and started
which is not enabling all possible configuration based on user request.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00
Michal Simek
71c52f2949 microblaze: Remove unused XILINX_BOARD_NAME macro
This macro is not used anywhere that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:54 +02:00
Michal Simek
d6c856c008 microblaze: Guard do_reset by CONFIG_SYSRESET
sysreset uclass have own do_reset function which should be used instead
of board/platform specific.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:54 +02:00
Siva Durga Prasad Paladugu
37e3a36a54 xilinx: zynq: Add support to secure images
This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
   authenticated or encrypted or both authenticated and encrypted
   image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
   image back to DDR as per destination address. The image has
   to be encrypted using xilinx bootgen tool and to get only the
   encrypted image from tool use -split option while invoking
   bootgen.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:54 +02:00
Luca Ceresoli
6da4f67ad0 arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variable
U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on
ZynqMP (PS init for short). The current logic to locate this file for
both platforms is:

 1. if a board-specific file exists in
    board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c
    then use it
 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c

In the latter case the file does not exist in the U-Boot sources and
must be copied in the source tree from the outside before starting the
build. This is typical when it is generated from Xilinx tools while
developing a custom hardware. However making sure that a
board-specific file is _not_ found (and used) requires some trickery
such as removing or overwriting all PS init files (e.g.: the current
meta-xilinx yocto layer).

This generates a few problems:

 * if the source tree is shared among different out-of-tree builds,
   they will pollute (and potentially corrupt) each other
 * the source tree cannot be read-only
 * any buildsystem must add a command to copy the PS init file binary
 * overwriting or deleting files in the source tree is ugly as hell

Simplify usage by allowing to pass the path to the desired PS init
file in kconfig variable XILINX_PS_INIT_FILE. It can be an absolute
path or relative to $(srctree). If the variable is set, the
user-specified file will always be used without being copied
around. If the the variable is left empty, for backward compatibility
fall back to the old behaviour.

Since the issue is the same for Zynq and ZynqMP, add one kconfig
variable in a common place and use it for both.

Also use the new kconfig help text to document all the ways to give
U-Boot the PS init file.

Build-tested with all combinations of:
 - platform: zynq or zynqmp
 - PS init file: from XILINX_PS_INIT_FILE (absolute, relative path,
   non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/
 - building in-tree, in subdir, in other directory

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:53 +02:00
Michal Simek
1e3e68f109 arm64: zynqmp: Check return value from calloc
calloc() can fail and return NULL. The patch is checking return value
and return in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Michal Simek
0ecd14e636 arm: zynq: Add missing watchdog header
Add missing header detected by sparse.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Michal Simek
2882b39d56 arm64: zynqmp: Setup the first boot_target at run time
Detect mmc alias at run time for setting up proper boot_targets sequence.
The first target has to correspond with boot mode.

The purpose of this patch is to get rid of CONFIG_ZYNQ_SDHCI0/1
parameters in full U-Boot.
Unfortunately this patch can't remove it because there is missing
mmc implementation for SPL_DM_SEQ_ALIAS.

Also xilinx_zynqmp.h only setup boot commands for mmc0 and mmc1.
It means using aliases with higher number won't work. But switching
between mmc0 and mmc1 should work properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-05-31 13:50:39 +02:00
Michal Simek
d348beaa63 arm64: zynqmp: Show reset reason
Read reset reason reg and show it in log and also save it as variable.
Clearing reset reason when it is read to show only one status

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00
Michal Simek
b4af64fdfd arm64: zynqmp: Use DWC3 generic driver and DM_USB
Remove harcoded XHCI lists and detect mode, speed based on DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Serial-changes: 2
- Remove also XHCI macros from hardware.h
- Remove additional new line in zcu106
2018-05-18 13:23:15 +02:00
Tom Rini
57a72d0560 SPDX: Correct SPDX tags from recent xilinx merge
Correct the SPDX tag format.

Fixes: 3b52847a45 ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-11 14:54:57 -04:00
Tom Rini
3b52847a45 Xilinx changes for v2018.07
microblaze:
 - Align defconfig
 
 zynq:
 - Rework fpga initialization and cpuinfo handling
 
 zynqmp:
 - Add ZynqMP R5 support
 - Wire and enable watchdog on zcu100-revC
 - Setup MMU map for DDR at run time
 - Show board info based on DT and cleanup IDENT_STRING
 
 zynqmp tools:
 - Add read partition support
 - Add initial support for Xilinx bif format for boot.bin generation
 
 mmc:
 - Fix get_timer usage on 64bit cpus
 - Add support for SD3.0 UHS mode
 
 nand-zynq:
 - Add support for 16bit buswidth
 - Use address cycles from onfi params
 
 scsi:
 - convert ceva sata to UCLASS_AHCI
 
 timer:
 - Add Cadence TTC for ZynqMP r5
 
 watchdog:
 - Minor cadence driver cleanup
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Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup
2018-05-11 11:45:28 -04:00
Siva Durga Prasad Paladugu
d1f4e39d58 mmc: zynq_sdhci: Add support for SD3.0
This patch adds support of SD3.0 for ZynqMP.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 11:13:51 +02:00
Michal Simek
1d6c54ecb3 arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5>

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:38:23 +02:00
Michal Simek
0478b0b9b6 arm64: zynqmp: Simplify boot_target variable composition
Call calloc for space allocation only at one location and include if/else
to sprintf. This will simplify run time device adding based on id aliases.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-05-11 09:23:43 +02:00
Nitin Jain
0678941ae5 arm64: zynqmp: Setup MMU map for DDR at run time
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.

The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.

Signed-off-by: Nitin Jain <nitin.jain@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
4490e013ee arm64: zynqmp: Wire watchdog internals
Enable watchdog in full U-Boot.

Similar changes were done by:
"arm: zynq: Wire watchdog internals"
(sha1: e6cc3b25d7)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
e00656b2a9 arm64: zynqmp: Reset FPD Watchdog on zcu100
Low level configuration didn't reset FPD Watchdog that's why accessing
it caused u-boot hang.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Siva Durga Prasad Paladugu
04ab29ab25 arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
0b4b82ad14 arm: zynq: Remove checkboard and enable DISPLAY_CPUINFO
Now that showing silicon version is part of the CPU
info display, let's remove checkboard().

Note that the generic show_board_info() will still
show the DT 'model' property. For instance:

U-Boot 2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200)

CPU:   Zynq 7z045
Silicon: v1.0
Model: Zynq ZC706 Development Board
I2C:   ready

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>,
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

mini configuration doesn't need to show this information.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Michal Simek
4aba5fb857 arm: zynq: Rework FPGA initialization
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-11 09:23:43 +02:00
Tom Rini
f739fcd831 SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed.  These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict.  This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.

Fixes: 83d290c56f ("SPDX: Convert all of our single license tags to Linux Kernel style")
Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-10 20:38:35 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Michal Simek
61dc92a29d arm: zynq: Wire automatic ddr detection for Zynq and ZynqMP case
When static memory configuration is used U-Boot has capability to detect
memory size in setup range. Enable this feature for static
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
cf0bcd7d02 arm64: zynqmp: Add support for Xilinx zcu106-revA
Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:52 +02:00