Michal Simek fdba86972f ARM: zynq: Wire SPL configuration for cse nor/nand targets ... These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2018-11-29 10:31:02 +01:00
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microblaze-generic	microblaze: Use standard functions for memory decoding	2018-11-26 10:50:55 +01:00
versal	arm64: versal: Add support for new Xilinx Versal ACAPs	2018-10-16 16:53:21 +02:00
zynq	ARM: zynq: Wire SPL configuration for cse nor/nand targets	2018-11-29 10:31:02 +01:00
zynqmp	arm64: zynqmp: Fix logic in CG/EG/EV detection	2018-11-26 10:50:54 +01:00
zynqmp_r5	lib: fdtdec: Rename routine fdtdec_setup_memory_size()	2018-07-19 10:49:56 +02:00
Kconfig	arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variable	2018-07-19 10:49:53 +02:00