Commit graph

80696 commits

Author SHA1 Message Date
Joel Stanley
a7d606ff61 mmc/aspeed: Enable controller clocks
Request and enable the controller level clocks.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
66900bc254 mmc/aspeed: Probe from controller
The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.

Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:

    ofnode node;

    dev_for_each_subnode(node, parent) {
    	struct udevice *dev;
    	int ret;

    	ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
    					 ofnode_get_name(node),
    					 node, &dev);
    	if (ret)
    		return ret;
    }

However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.

Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.

Select MISC as the controller driver is implemented as a misc device.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
f49a7a160d mmc/aspeed: Add debuging for clock probe failures
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
50204533dc clk/ast2500: Add SD clock
In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
85bb3a4eee clk/ast2600: Adjust eMMC clock names
Adjust clock to stay compatible with those used by the Linux kernel
device tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
67e20f9d65 clk/aspeed: Add debug message when clock fails
A common message across platforms that prints the clock number.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
0b2a749bc6 ARM: dts: ast2500: Update SDHCI nodes
Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
dedf8e3186 ARM: dts: ast2600: Update SDHCI nodes
Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
f760403f83 config/aspeed: Enable EEPROM options
To allow testing of the I2C driver, enable the eprom command and the
misc driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:31:29 -04:00
Joel Stanley
93330f2823 config/ast2600: Enable I2C driver
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Joel Stanley
50b23b1c5b i2c/aspeed: Add AST2600 compatible
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
453fe1eece i2c/aspeed: Fix reset control
The reset control was written for the ast2500 and directly programs the
clocking register.

So we can share the code with other SoC generations use the reset device
to deassert the I2C reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
0a8bd97f88 reset/aspeed: Implement status callback
The I2C driver shares a reset line between buses, so allow it to test
the state of the reset line before resetting it.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
b45768ebfe ARM: dts: ast2600-evb: Add I2C devices
The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7,
and a LM75 temp sensor on bus 8.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Joel Stanley
5ff466fade ARM: dts: ast2500-evb: Add I2C devices
The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
3ad1d85d3c ARM: dts: ast2600-evb: Remove redundant pinctrl
Now that these are in the dtsi we don't need them in the EVB device
tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Joel Stanley
fc28e02404 ARM: dts: ast2600: Disable I2C nodes by default
Allow boards to enable the buses they use.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Joel Stanley
a87273bc40 ARM: dts: ast2600: Add I2C reset properties
The same as the upstream Linux device tree, each i2c bus has a property
specifying the reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2022-07-06 14:30:51 -04:00
Eddie James
8c3019216e ARM: dts: ast2600: Add I2C pinctrl
Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-07-06 14:30:51 -04:00
Bryan Brattlof
10c8bafbc3 soc: soc_ti_k3: identify j7200 SR2.0 SoCs
Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.

Rather than defining a revision string array for each SoC, use a
default revision string array for all TI SoCs that continue to follow
the typical 1.0 -> 2.0 revision scheme.

Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-07-06 14:30:51 -04:00
Jim Liu
fdd08f896b phy: nuvoton: add NPCM7xx phy control driver
add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-07-06 14:30:51 -04:00
Philippe Schenker
1cf4e79f57 toradex: tdx-cfg-block: add new toradex oui range
Add new Toradex MAC OUI (8c:06:cb), to the config block. With this change
we extend the possible serial-numbers as follows:

For serial-numbers 00000000-16777215 OUI 00:14:2d is taken
For serial-numbers 16777216-33554431 OUI 8c:06:cb is taken

Lower 24-bit of the serial number are used in the NIC part of the
MAC address, the complete serial number can be calculated using the OUI.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-06 14:30:51 -04:00
Nishanth Menon
a58147c2db board: ti: common: board_detect: Do 1byte address checks first.
Do 1 byte address checks first prior to doing 2 byte address checks.
When performing 2 byte addressing on 1 byte addressing eeprom, the
second byte is taken in as a write operation and ends up erasing the
eeprom region we want to preserve.

While we could have theoretically handled this by ensuring the write
protect of the eeproms are properly managed, this is not true in case
where board are updated with 1 byte eeproms to handle supply status.

Flipping the checks by checking for 1 byte addressing prior to 2 byte
addressing check prevents this problem at the minor cost of additional
overhead for boards with 2 byte addressing eeproms.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Nishanth Menon
bc1de48371 board: ti: common: Handle the legacy eeprom address width properly
Due to supply chain issues, we are starting to see a mixture of eeprom
usage including the smaller 7-bit addressing eeproms such as 24c04
used for eeproms.

These eeproms don't respond well to 2 byte addressing and fail the
read operation. We do have a check to ensure that we are reading the
alternate addressing size, however the valid failure prevents us
from checking at 1 byte anymore.

Rectify the same by falling through and depend on header data comparison
to ensure that we have valid data.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Nishanth Menon
8b5218e7cb board: ti: common: Optimize boot when detecting consecutive bad records
The eeprom data area is much bigger than the data we intend to store,
however, with bad programming, we might end up reading bad records over
and over till we run out of eeprom space. instead just exit when 10
consecutive records are read.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Vignesh Raghavendra
e4b4501ede firmware: ti_sci_static_data: Make file board agnostic
Static DMA channel data for R5 SPL is mostly board agnostic so use SOC
configs instead of EVM specific config to ease adding new board support.

Drop J7200 EVM specific settings as its same as J721e

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
6ea5bcc4a6 configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is
needed to calculate the size of DDR that is available.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
4c092bb306 board: ti: am62x: Account for DDR size fixups if ECC is enabled
Call into k3-ddrss driver to fixup device tree and resize
the available amount of DDR if ECC is enabled.

A second fixup is required from A53 SPL to take the fixup
as done from R5 SPL and apply it to DT passed to A53 U-boot,
which in turn passes this to the OS.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
249e9f3d19 board: ti: am62x: Use fdt functions for ram and bank init
Use the appropriate fdtdec_setup_mem_size_base() call in
dram_init() and fdtdec_setup_bank_size() in dram_bank_init()
to pull these values from DT, where they are already available,
instead of hardcoding them.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
362b0d2e6e arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl
Mark the memory node with u-boot,dm-spl so we can use it
from early SPL on both R5 and A53.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Georgi Vlaev
a04bbb83b4 arm: mach-k3: common: Use ddr_init in spl_enable_dcache
The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size. Normally the dram_init_banksize()
setups the memory banks, while the total size is reported
by ddr_init(). This worked so far for K3 since we set the
gd->ram_size in dram_init_banksize() as well.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Philippe Schenker
7e27ce16c5 toradex: tdx-cfg-block: extend assembly version
There are two decimal digits reserved to encode the module version and
revision. This code so far implemented A-Z which used 0-25 of this
range.
This commit extends the range to make use of all 99 numbers. After
capital letters the form with a hashtag and number (e.g. #26) is used.

Examples:

If the assembly version is between zero and 25 the numbering is as follows,
as it also has been before this commit:
0: V0.0A
1: V0.0B
...
25: V0.0Z

New numbering of assembly version:
If the number is between 26 and 99 the new assembly version name is:
26: V0.0#26
27: V0.0#27
...
99: V0.0#99

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-06 14:30:08 -04:00
Philippe Schenker
494ef10c3b toradex: tdx-cfg-block: use defines for string length
With those defines the length can be reused and is in one place
extendable.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-06 14:30:08 -04:00
Philippe Schenker
39ff0624bc toradex: tdx-cfg-block: use only snprintf
Prevent memory issues that could appear with sprintf. Replace all
sprintf occurences with snprintf.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-07-06 14:30:08 -04:00
Aswath Govindraju
e0392596e9 board: ti: j721e: Return if there is an error while configuring SerDes
While configuring SerDes, errors could be encountered, in these cases,
return instead of going ahead. This is will help in booting even if
configuration of SerDes fails.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-07-06 14:30:08 -04:00
Vaishnav Achath
c16b4f14a3 arm: k3: j721e: add dynamic sf bus override support for j721e
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2022-07-06 14:30:08 -04:00
Vaishnav Achath
6dd18a6568 common: spl: spl_spi: add support for dynamic override of sf bus
Currently the SPI flash to load from is defined through the compile
time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this
prevents the loading of binaries from different SPI flash using the
same build.E.g. supporting QSPI flash boot and OSPI flash boot
on J721E platform is not possible due to this limitation.

This commit adds lookup functions spl_spi_boot_bus()
and spl_spi_boot_cs for identifying the flash device based on the
selected boot device, when not overridden the lookup functions are
weakly defined in common/spl/spl_spi.c.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-07-06 14:30:08 -04:00
Tom Rini
2d2c61ff04 Pull request efi-2022-07-rc7
UEFI:
 
 * correct verification of signed UEFI binaries
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Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2022-07-rc7

UEFI:

* correct verification of signed UEFI binaries
2022-07-06 09:17:08 -04:00
Tom Rini
4b7d0b24c7 Merge branch '2022-07-05-more-Kconfig-migrations' into next
- Migrate more CONFIG symbols to Kconfig, remove some dead code and
  clean-up arch/Kconfig.nxp slightly more.
2022-07-06 09:15:36 -04:00
Tom Rini
432243cee1 Convert CONFIG_KIRKWOOD_PCIE_INIT et al to Kconfig
This converts the following to Kconfig:
   CONFIG_KIRKWOOD_EGIGA_INIT
   CONFIG_KIRKWOOD_PCIE_INIT
   CONFIG_KIRKWOOD_RGMII_PAD_1V8
   CONFIG_KM_DISABLE_PCIE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
604c62f511 qemu-ppce500: Move CONFIG_SYS_PCI_MAP_{START, END} to board code
These CONFIG options are only used on this board, in the board file
itself.  Remove these from the CONFIG namespace and define in the board
file.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
6bb74fe19b Convert CONFIG_SYS_FSL_PCI_VER_3_X to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_PCI_VER_3_X

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
363397ae1a Convert CONFIG_PCI_MSC01 to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_MSC01

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
1bc8ef4d70 socrates: Rework CONFIG_PCI_CLK_FREQ
The symbol CONFIG_PCI_CLK_FREQ is local to this board.  Provide equal
clarity in the code by referencing the numeric value directly and move
the explanatory comment to the code, just prior to use.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
31a8f5545e Convert CONFIG_SH7751_PCI to Kconfig
This converts the following to Kconfig:
   CONFIG_SH7751_PCI

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
9ee06d286a MPC837XERDB: Remove unused PCI defines
These defines aren't referenced in code today, remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:05:00 -04:00
Tom Rini
c55094f14d m68k: Remove unused PCI code
The only mcf5445x platform does not enable PCI, drop this code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
e58eebb514 Convert CONFIG_PCI_CONFIG_HOST_BRIDGE to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_CONFIG_HOST_BRIDGE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
bf2c48fa1a Convert CONFIG_PCI_GT64120 to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_GT64120

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00
Tom Rini
f27bca4c27 Convert CONFIG_PCI_SCAN_SHOW to Kconfig
This converts the following to Kconfig:
   CONFIG_PCI_SCAN_SHOW

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:04:59 -04:00