mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 23:07:00 +00:00
Merge branch '2022-07-05-more-Kconfig-migrations' into next
- Migrate more CONFIG symbols to Kconfig, remove some dead code and clean-up arch/Kconfig.nxp slightly more.
This commit is contained in:
Tom Rini
commit
4b7d0b24c7
373 changed files with 1448 additions and 1509 deletions
29
README
29
README
|
|
@ -388,10 +388,6 @@ The following options need to be configured:
|
|||
CONFIG_SYS_FSL_DDR_ADDR
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||||
Freescale DDR memory-mapped register base.
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||||
|
||||
CONFIG_SYS_FSL_DDR_EMU
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||||
Specify emulator support for DDR. Some DDR features such as
|
||||
deskew training are not available.
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||||
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||||
CONFIG_SYS_FSL_DDRC_GEN1
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Freescale DDR1 controller.
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||||
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||||
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|
@ -1306,11 +1302,6 @@ The following options need to be configured:
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|||
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will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
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||||
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CONFIG_SYS_SPD_BUS_NUM
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If defined, then this indicates the I2C bus number for DDR SPD.
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If not defined, then U-Boot assumes that SPD is on I2C bus 0.
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CONFIG_SYS_RTC_BUS_NUM
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If defined, then this indicates the I2C bus number for the RTC.
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@ -1518,20 +1509,6 @@ The following options need to be configured:
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|||
overwriting the architecture dependent default
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settings.
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||||
- Frame Buffer Address:
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CONFIG_FB_ADDR
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Define CONFIG_FB_ADDR if you want to use specific
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||||
address for frame buffer. This is typically the case
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when using a graphics controller has separate video
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||||
memory. U-Boot will then place the frame buffer at
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the given address instead of dynamically reserving it
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in system RAM by calling lcd_setmem(), which grabs
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the memory for the frame buffer depending on the
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||||
configured panel size.
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Please see board_init_f function.
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- Automatic software updates via TFTP server
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CONFIG_UPDATE_TFTP
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CONFIG_UPDATE_TFTP_CNT_MAX
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@ -2088,12 +2065,6 @@ Low Level (hardware related) configuration options:
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one, specify here. Note that the value must resolve
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to something your driver can deal with.
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- CONFIG_SYS_DDR_RAW_TIMING
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Get DDR timing information from other than SPD. Common with
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soldered DDR chips onboard without SPD. DDR raw timing
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parameters are extracted from datasheet and hard-coded into
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header files or board specific files.
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- CONFIG_FSL_DDR_INTERACTIVE
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Enable interactive DDR debugging. See doc/README.fsl-ddr.
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@ -451,6 +451,12 @@ source "arch/x86/Kconfig"
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source "arch/xtensa/Kconfig"
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source "arch/riscv/Kconfig"
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if ARM || M68K || PPC
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source "arch/Kconfig.nxp"
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endif
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source "board/keymile/Kconfig"
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if MIPS || MICROBLAZE
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|
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240
arch/Kconfig.nxp
Normal file
240
arch/Kconfig.nxp
Normal file
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@ -0,0 +1,240 @@
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config NXP_ESBC
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bool "NXP ESBC (secure boot) functionality"
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help
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Enable Freescale Secure Boot feature. Normally selected by defconfig.
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If unsure, do not change.
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menu "Chain of trust / secure boot options"
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depends on !FIT_SIGNATURE && NXP_ESBC
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config CHAIN_OF_TRUST
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select FSL_CAAM
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select ARCH_MISC_INIT
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select FSL_SEC_MON
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select SPL_BOARD_INIT if (ARM && SPL)
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select SPL_HASH if (ARM && SPL)
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select SHA_HW_ACCEL
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select SHA_PROG_HW_ACCEL
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select ENV_IS_NOWHERE
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select CMD_EXT4 if ARM
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select CMD_EXT4_WRITE if ARM
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imply CMD_BLOB
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imply CMD_HASH if ARM
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def_bool y
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config CMD_ESBC_VALIDATE
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bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
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default y
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help
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This option enables two commands used for secure booting:
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esbc_validate - validate signature using RSA verification
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||||
esbc_halt - put the core in spin loop (Secure Boot Only)
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config ESBC_HDR_LS
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bool
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config ESBC_ADDR_64BIT
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def_bool y
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depends on ESBC_HDR_LS && FSL_LAYERSCAPE
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help
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||||
For Layerscape based platforms, ESBC image Address in Header is 64bit.
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config SYS_FSL_SFP_BE
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def_bool y
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depends on PPC || FSL_LSCH2 || ARCH_LS1021A
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config SYS_FSL_SFP_LE
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def_bool y
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depends on !SYS_FSL_SFP_BE
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choice
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prompt "SFP IP revision"
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default SYS_FSL_SFP_VER_3_0 if PPC
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default SYS_FSL_SFP_VER_3_4
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config SYS_FSL_SFP_VER_3_0
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bool "SFP version 3.0"
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config SYS_FSL_SFP_VER_3_2
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bool "SFP version 3.2"
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config SYS_FSL_SFP_VER_3_4
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bool "SFP version 3.4"
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endchoice
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config SPL_UBOOT_KEY_HASH
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string "Non-SRK key hash for U-Boot public/private key pair"
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depends on SPL
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||||
default ""
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||||
help
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||||
Set the key hash for U-Boot here if public/private key pair used to
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||||
sign U-boot are different from the SRK hash put in the fuse. Example
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||||
of a key hash is
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||||
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
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||||
Otherwise leave this empty.
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if PPC
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config BOOTSCRIPT_COPY_RAM
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bool "Secure boot copies boot script to RAM"
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help
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On systems that support chain of trust booting, a number of addresses
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are required to set variables that are used in the copying and then
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verification of different parts of the system. If enabled, the subsequent
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options are for what location to use in each step.
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||||
config BS_ADDR_DEVICE
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hex "Address in RAM for bs_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_SIZE
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hex "The size of bs_size which is the amount read from bs_device"
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depends on BOOTSCRIPT_COPY_RAM
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config BS_ADDR_RAM
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hex "Address in RAM for bs_ram"
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depends on BOOTSCRIPT_COPY_RAM
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||||
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||||
config BS_HDR_ADDR_DEVICE
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hex "Address in RAM for bs_hdr_device"
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depends on BOOTSCRIPT_COPY_RAM
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||||
config BS_HDR_SIZE
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hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
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depends on BOOTSCRIPT_COPY_RAM
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||||
config BS_HDR_ADDR_RAM
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hex "Address in RAM for bs_hdr_ram"
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depends on BOOTSCRIPT_COPY_RAM
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config BOOTSCRIPT_HDR_ADDR
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hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
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||||
default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
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||||
endif
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config SYS_FSL_SRK_LE
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||||
def_bool y
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depends on ARM
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||||
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||||
config KEY_REVOCATION
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def_bool y
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||||
endmenu
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||||
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||||
comment "Other functionality shared between NXP SoCs"
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||||
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||||
config DEEP_SLEEP
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bool "Enable SoC deep sleep feature"
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depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
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||||
default y
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||||
help
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||||
Indicates this SoC supports deep sleep feature. If deep sleep is
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||||
supported, core will start to execute uboot when wakes up.
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||||
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||||
config LAYERSCAPE_NS_ACCESS
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||||
bool "Layerscape non-secure access support"
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||||
depends on ARCH_LS1021A || FSL_LSCH2
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||||
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||||
config PCIE1
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||||
bool "PCIe controller #1"
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||||
depends on LAYERSCAPE_NS_ACCESS || PPC
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||||
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config PCIE2
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bool "PCIe controller #2"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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||||
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||||
config PCIE3
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bool "PCIe controller #3"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config PCIE4
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bool "PCIe controller #4"
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depends on LAYERSCAPE_NS_ACCESS || PPC
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config FSL_USE_PCA9547_MUX
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bool "Enable PCA9547 I2C Mux on Freescale boards"
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depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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help
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This option enables the PCA9547 I2C mux on Freescale boards.
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||||
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||||
config VID
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bool "Enable Freescale VID"
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depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
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||||
help
|
||||
This option enables setting core voltage based on individual
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||||
values saved in SoC fuses.
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||||
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||||
config SPL_VID
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bool "Enable Freescale VID in SPL"
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depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
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help
|
||||
This option enables setting core voltage based on individual
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||||
values saved in SoC fuses, in SPL.
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if VID || SPL_VID
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config VID_FLS_ENV
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string "Environment variable for overriding VDD"
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help
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||||
This option allows for specifying the environment variable
|
||||
to check to override VDD information.
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config VOL_MONITOR_INA220
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bool "Enable the INA220 voltage monitor read"
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help
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||||
This option enables INA220 voltage monitor read
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functionality. It is used by the common VID driver.
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config VOL_MONITOR_IR36021_READ
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bool "Enable the IR36021 voltage monitor read"
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help
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This option enables IR36021 voltage monitor read
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functionality. It is used by the common VID driver.
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||||
config VOL_MONITOR_IR36021_SET
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bool "Enable the IR36021 voltage monitor set"
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help
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||||
This option enables IR36021 voltage monitor set
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||||
functionality. It is used by the common VID driver.
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||||
config VOL_MONITOR_LTC3882_READ
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bool "Enable the LTC3882 voltage monitor read"
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||||
help
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||||
This option enables LTC3882 voltage monitor read
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||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_LTC3882_SET
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bool "Enable the LTC3882 voltage monitor set"
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||||
help
|
||||
This option enables LTC3882 voltage monitor set
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_ISL68233_READ
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bool "Enable the ISL68233 voltage monitor read"
|
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help
|
||||
This option enables ISL68233 voltage monitor read
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_ISL68233_SET
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bool "Enable the ISL68233 voltage monitor set"
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help
|
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This option enables ISL68233 voltage monitor set
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
endif
|
||||
|
||||
config FSL_QIXIS
|
||||
bool "Enable QIXIS support"
|
||||
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
|
||||
|
||||
config QIXIS_I2C_ACCESS
|
||||
bool "Access to QIXIS is over i2c"
|
||||
depends on FSL_QIXIS
|
||||
default y
|
||||
|
||||
config HAS_FSL_DR_USB
|
||||
def_bool y
|
||||
depends on USB_EHCI_HCD && PPC
|
||||
|
|
@ -41,12 +41,6 @@ config MAX_CPUS
|
|||
cores, count the reserved ports. This will allocate enough memory
|
||||
in spin table to properly handle all cores.
|
||||
|
||||
config NXP_ESBC
|
||||
bool "NXP_ESBC"
|
||||
help
|
||||
Enable Freescale Secure Boot feature. Normally selected
|
||||
by defconfig. If unsure, do not change.
|
||||
|
||||
config SYS_CCI400_OFFSET
|
||||
hex "Offset for CCI400 base"
|
||||
depends on SYS_FSL_HAS_CCI400
|
||||
|
|
|
|||
|
|
@ -3,14 +3,13 @@
|
|||
# Copyright (C) 2009 Samsung Electronics
|
||||
# Minkyu Kang <mk7.kang@samsung.com>
|
||||
|
||||
obj-$(CONFIG_PWM_S5P) += pwm.o
|
||||
ifdef CONFIG_ARCH_NEXELL
|
||||
obj-$(CONFIG_PWM_NX) += pwm.o
|
||||
obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
|
||||
else
|
||||
obj-y += cpu_info.o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
obj-y += timer.o
|
||||
obj-y += sromc.o
|
||||
obj-$(CONFIG_PWM) += pwm.o
|
||||
endif
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ config ARCH_LS1012A
|
|||
config ARCH_LS1028A
|
||||
bool
|
||||
select ARMV8_SET_SMPEN
|
||||
select ESBC_HDR_LS if CHAIN_OF_TRUST
|
||||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
||||
select GICV3
|
||||
|
|
@ -138,6 +139,7 @@ config ARCH_LS1088A
|
|||
bool
|
||||
select ARMV8_SET_SMPEN
|
||||
select ARM_ERRATA_855873 if !TFABOOT
|
||||
select ESBC_HDR_LS if CHAIN_OF_TRUST
|
||||
select FSL_IFC
|
||||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
||||
|
|
@ -187,6 +189,7 @@ config ARCH_LS2080A
|
|||
select ARM_ERRATA_828024
|
||||
select ARM_ERRATA_829520
|
||||
select ARM_ERRATA_833471
|
||||
select ESBC_HDR_LS if CHAIN_OF_TRUST
|
||||
select FSL_IFC
|
||||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
||||
|
|
@ -239,6 +242,7 @@ config ARCH_LS2080A
|
|||
config ARCH_LX2162A
|
||||
bool
|
||||
select ARMV8_SET_SMPEN
|
||||
select ESBC_HDR_LS if CHAIN_OF_TRUST
|
||||
select FSL_DDR_BIST
|
||||
select FSL_DDR_INTERACTIVE
|
||||
select FSL_LAYERSCAPE
|
||||
|
|
@ -277,6 +281,7 @@ config ARCH_LX2162A
|
|||
config ARCH_LX2160A
|
||||
bool
|
||||
select ARMV8_SET_SMPEN
|
||||
select ESBC_HDR_LS if CHAIN_OF_TRUST
|
||||
select FSL_DDR_BIST
|
||||
select FSL_DDR_INTERACTIVE
|
||||
select FSL_LAYERSCAPE
|
||||
|
|
@ -456,11 +461,6 @@ config EMC2305
|
|||
Enable the EMC2305 fan controller for configuration of fan
|
||||
speed.
|
||||
|
||||
config NXP_ESBC
|
||||
bool "NXP_ESBC"
|
||||
help
|
||||
Enable Freescale Secure Boot feature
|
||||
|
||||
config QSPI_AHB_INIT
|
||||
bool "Init the QSPI AHB bus"
|
||||
help
|
||||
|
|
@ -511,6 +511,11 @@ config DP_DDR_CTRL
|
|||
depends on SYS_FSL_HAS_DP_DDR
|
||||
default 2 if ARCH_LS2080A
|
||||
|
||||
config DP_DDR_DIMM_SLOTS_PER_CTLR
|
||||
int
|
||||
depends on SYS_FSL_HAS_DP_DDR
|
||||
default 1 if ARCH_LS2080A
|
||||
|
||||
config DP_DDR_NUM_CTRLS
|
||||
int
|
||||
depends on SYS_FSL_HAS_DP_DDR
|
||||
|
|
|
|||
|
|
@ -55,17 +55,6 @@
|
|||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
|
|
@ -160,17 +149,6 @@
|
|||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
|
@ -215,17 +193,6 @@
|
|||
/* SMMU Definitions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
|
|
@ -274,20 +241,9 @@
|
|||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
|
|
@ -321,11 +277,6 @@
|
|||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
|
@ -361,11 +312,6 @@
|
|||
#elif defined(CONFIG_ARCH_LS1012A)
|
||||
#define GICD_BASE 0x01401000
|
||||
#define GICC_BASE 0x01402000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
|
@ -380,11 +326,6 @@
|
|||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
/* SMMU Defintions */
|
||||
#define SMMU_BASE 0x09000000
|
||||
|
|
|
|||
|
|
@ -87,10 +87,6 @@
|
|||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
#define DCU_LAYER_MAX_NUM 16
|
||||
|
||||
|
|
|
|||
|
|
@ -8,31 +8,6 @@
|
|||
#define __FSL_SECURE_BOOT_H
|
||||
|
||||
#ifdef CONFIG_CHAIN_OF_TRUST
|
||||
#define CONFIG_FSL_SEC_MON
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* Define the key hash for U-Boot here if public/private key pair used to
|
||||
* sign U-boot are different from the SRK hash put in the fuse
|
||||
* Example of defining KEY_HASH is
|
||||
* #define CONFIG_SPL_UBOOT_KEY_HASH \
|
||||
* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
|
||||
* else leave it defined as NULL
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
|
||||
#endif /* ifdef CONFIG_SPL_BUILD */
|
||||
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
|
||||
#if defined(CONFIG_FSL_LAYERSCAPE)
|
||||
/*
|
||||
* For fsl layerscape based platforms, ESBC image Address in Header
|
||||
* is 64 bit.
|
||||
*/
|
||||
#define CONFIG_ESBC_ADDR_64BIT
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* The key used for verification of next level images
|
||||
|
|
@ -49,76 +24,6 @@
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_LS2080A
|
||||
#define CONFIG_EXTRA_ENV \
|
||||
"setenv fdt_high 0xa0000000;" \
|
||||
"setenv initrd_high 0xcfffffff;" \
|
||||
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV \
|
||||
"setenv fdt_high 0xffffffff;" \
|
||||
"setenv initrd_high 0xffffffff;" \
|
||||
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
|
||||
#endif
|
||||
|
||||
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
|
||||
* Non-XIP Memory (Nand/SD)*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
|
||||
defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_BOOTSCRIPT_COPY_RAM
|
||||
#endif
|
||||
/* The address needs to be modified according to NOR, NAND, SD and
|
||||
* DDR memory map
|
||||
*/
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x20600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000
|
||||
#else /* NOR BOOT */
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x580600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
|
||||
#endif /*ifdef CONFIG_QSPI_BOOT */
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00004000
|
||||
#define CONFIG_BS_ADDR_RAM 0xa0600000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
|
||||
#else
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
/* For SD boot address and size are assigned in terms of sector
|
||||
* offset and no. of sectors respectively.
|
||||
*/
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00003000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
|
||||
#define CONFIG_BS_SIZE 0x00000008
|
||||
#define CONFIG_BS_HDR_SIZE 0x00000010
|
||||
#elif defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#elif defined(CONFIG_QSPI_BOOT)
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x40600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#else /* Default NOR Boot */
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x60600000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#endif
|
||||
#define CONFIG_BS_ADDR_RAM 0x81000000
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
|
||||
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
|
||||
#else
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
|
||||
/* BOOTSCRIPT_ADDR is not required */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA
|
||||
/* Define the key hash here if SRK used for signing PPA image is
|
||||
* different from SRK hash put in SFP used for U-Boot.
|
||||
|
|
@ -129,7 +34,6 @@
|
|||
#define PPA_KEY_HASH NULL
|
||||
#endif /* ifdef CONFIG_FSL_LS_PPA */
|
||||
|
||||
#include <config_fsl_chain_trust.h>
|
||||
#endif /* #ifndef CONFIG_SPL_BUILD */
|
||||
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -121,6 +121,18 @@ endchoice
|
|||
config SYS_SOC
|
||||
default "kirkwood"
|
||||
|
||||
config KIRKWOOD_RGMII_PAD_1V8
|
||||
bool "Configures the I/O voltage of the pads connected gigabit interface to 1.8V"
|
||||
default y
|
||||
|
||||
config KIRKWOOD_EGIGA_INIT
|
||||
bool "Enable GbePort0/1 for kernel"
|
||||
default y
|
||||
|
||||
config KIRKWOOD_PCIE_INIT
|
||||
bool "Enable PCIe Port0 for kernel"
|
||||
default y
|
||||
|
||||
source "board/Marvell/openrd/Kconfig"
|
||||
source "board/Marvell/dreamplug/Kconfig"
|
||||
source "board/Synology/ds109/Kconfig"
|
||||
|
|
|
|||
|
|
@ -23,9 +23,6 @@
|
|||
#endif /* CONFIG_KW88F6281 */
|
||||
|
||||
#include <asm/arch/soc.h>
|
||||
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
|
||||
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
|
||||
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
|
||||
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
|
||||
#define MV_UART_CONSOLE_BASE KW_UART0_BASE
|
||||
|
|
|
|||
|
|
@ -6,4 +6,4 @@
|
|||
# ccflags-y += -DET_DEBUG
|
||||
|
||||
extra-y = start.o
|
||||
obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
|
||||
obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
|
||||
|
|
|
|||
|
|
@ -1,151 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI Configuration space access support
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/* System RAM mapped over PCI */
|
||||
#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
|
||||
|
||||
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
|
||||
#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
|
||||
|
||||
#define PCI_OP(rw, size, type, op, mask) \
|
||||
int pci_##rw##_cfg_##size(struct pci_controller *hose, \
|
||||
pci_dev_t dev, int offset, type val) \
|
||||
{ \
|
||||
u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \
|
||||
PCI_FUNC(dev), offset); \
|
||||
out_be32(hose->cfg_addr, addr); \
|
||||
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
|
||||
out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
PCI_OP(read, byte, u8 *, in_8, 3)
|
||||
PCI_OP(read, word, u16 *, in_le16, 2)
|
||||
PCI_OP(read, dword, u32 *, in_le32, 0)
|
||||
PCI_OP(write, byte, u8, out_8, 3)
|
||||
PCI_OP(write, word, u16, out_le16, 2)
|
||||
PCI_OP(write, dword, u32, out_le32, 0)
|
||||
|
||||
void pci_mcf5445x_init(struct pci_controller *hose)
|
||||
{
|
||||
pci_t *pci = (pci_t *)MMAP_PCI;
|
||||
pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
|
||||
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
||||
u32 barEn = 0;
|
||||
|
||||
out_be32(&pciarb->acr, 0x001f001f);
|
||||
|
||||
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
|
||||
PCIREQ2, PCIGNT2 */
|
||||
out_be16(&gpio->par_pci,
|
||||
GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
|
||||
GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
|
||||
GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
|
||||
GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
|
||||
|
||||
/* Assert reset bit */
|
||||
setbits_be32(&pci->gscr, PCI_GSCR_PR);
|
||||
|
||||
setbits_be32(&pci->tcr1, PCI_TCR1_P);
|
||||
|
||||
/* Initiator windows */
|
||||
out_be32(&pci->iw0btar,
|
||||
CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
|
||||
out_be32(&pci->iw1btar,
|
||||
CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
|
||||
out_be32(&pci->iw2btar,
|
||||
CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
|
||||
|
||||
out_be32(&pci->iwcr,
|
||||
PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
|
||||
PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
|
||||
|
||||
out_be32(&pci->icr, 0);
|
||||
|
||||
/* Enable bus master and mem access */
|
||||
out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
|
||||
|
||||
/* Cache line size and master latency */
|
||||
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
|
||||
out_be32(&pci->cr2, 0);
|
||||
|
||||
#ifdef CONFIG_SYS_PCI_BAR0
|
||||
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
|
||||
out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B0E;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR1
|
||||
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
|
||||
out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B1E;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR2
|
||||
out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
|
||||
out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B2E;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR3
|
||||
out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
|
||||
out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B3E;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR4
|
||||
out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
|
||||
out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B4E;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR5
|
||||
out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
|
||||
out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
|
||||
barEn |= PCI_TCR2_B5E;
|
||||
#endif
|
||||
|
||||
out_be32(&pci->tcr2, barEn);
|
||||
|
||||
/* Deassert reset bit */
|
||||
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
|
||||
udelay(1000);
|
||||
|
||||
/* Enable PCI bus master support */
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
|
||||
CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
|
||||
|
||||
pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
|
||||
CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
|
||||
|
||||
pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
|
||||
CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->cfg_addr = &(pci->car);
|
||||
hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
|
||||
|
||||
pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
|
||||
pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
|
||||
pci_write_cfg_dword);
|
||||
|
||||
/* Hose scan */
|
||||
pci_register_hose(hose);
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
@ -187,6 +187,7 @@ config ARCH_B4420
|
|||
select E500MC
|
||||
select E6500
|
||||
select FSL_LAW
|
||||
select HETROGENOUS_CLUSTERS
|
||||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A004477
|
||||
select SYS_FSL_ERRATUM_A005871
|
||||
|
|
@ -195,7 +196,7 @@ config ARCH_B4420
|
|||
select SYS_FSL_ERRATUM_A006475
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
select SYS_FSL_ERRATUM_A007075
|
||||
select SYS_FSL_ERRATUM_A007186
|
||||
select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
|
||||
select SYS_FSL_ERRATUM_A007212
|
||||
select SYS_FSL_ERRATUM_A009942
|
||||
select SYS_FSL_HAS_DDR3
|
||||
|
|
@ -214,6 +215,7 @@ config ARCH_B4860
|
|||
select E500MC
|
||||
select E6500
|
||||
select FSL_LAW
|
||||
select HETROGENOUS_CLUSTERS
|
||||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A004477
|
||||
select SYS_FSL_ERRATUM_A005871
|
||||
|
|
@ -222,7 +224,7 @@ config ARCH_B4860
|
|||
select SYS_FSL_ERRATUM_A006475
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
select SYS_FSL_ERRATUM_A007075
|
||||
select SYS_FSL_ERRATUM_A007186
|
||||
select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
|
||||
select SYS_FSL_ERRATUM_A007212
|
||||
select SYS_FSL_ERRATUM_A007907
|
||||
select SYS_FSL_ERRATUM_A009942
|
||||
|
|
@ -733,7 +735,7 @@ config ARCH_T2080
|
|||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A006379
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
select SYS_FSL_ERRATUM_A007186
|
||||
select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
|
||||
select SYS_FSL_ERRATUM_A007212
|
||||
select SYS_FSL_ERRATUM_A007815
|
||||
select SYS_FSL_ERRATUM_A007907
|
||||
|
|
@ -766,7 +768,7 @@ config ARCH_T4240
|
|||
select SYS_FSL_ERRATUM_A006261
|
||||
select SYS_FSL_ERRATUM_A006379
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
select SYS_FSL_ERRATUM_A007186
|
||||
select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
|
||||
select SYS_FSL_ERRATUM_A007798
|
||||
select SYS_FSL_ERRATUM_A007815
|
||||
select SYS_FSL_ERRATUM_A007907
|
||||
|
|
@ -822,11 +824,8 @@ config FSL_LAW
|
|||
help
|
||||
Use Freescale common code for Local Access Window
|
||||
|
||||
config NXP_ESBC
|
||||
bool "NXP_ESBC"
|
||||
help
|
||||
Enable Freescale Secure Boot feature. Normally selected
|
||||
by defconfig. If unsure, do not change.
|
||||
config HETROGENOUS_CLUSTERS
|
||||
bool
|
||||
|
||||
config MAX_CPUS
|
||||
int "Maximum number of CPUs permitted for MPC85xx"
|
||||
|
|
@ -1121,6 +1120,35 @@ config SYS_NUM_TLBCAMS
|
|||
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
|
||||
16 for other E500 SoCs.
|
||||
|
||||
if HETROGENOUS_CLUSTERS
|
||||
|
||||
config SYS_MAPLE
|
||||
def_bool y
|
||||
|
||||
config SYS_CPRI
|
||||
def_bool y
|
||||
|
||||
config PPC_CLUSTER_START
|
||||
int
|
||||
default 0
|
||||
|
||||
config DSP_CLUSTER_START
|
||||
int
|
||||
default 1
|
||||
|
||||
config SYS_CPRI_CLK
|
||||
int
|
||||
default 3
|
||||
|
||||
config SYS_ULB_CLK
|
||||
int
|
||||
default 4
|
||||
|
||||
config SYS_ETVPE_CLK
|
||||
int
|
||||
default 1
|
||||
endif
|
||||
|
||||
config BACKSIDE_L2_CACHE
|
||||
bool
|
||||
|
||||
|
|
@ -1185,6 +1213,9 @@ config SYS_FSL_LBC_CLK_DIV
|
|||
Defines divider of platform clock(clock input to
|
||||
eLBC controller).
|
||||
|
||||
config ENABLE_36BIT_PHYS
|
||||
bool "Enable 36bit physical address space support"
|
||||
|
||||
config SYS_MPC85XX_NO_RESETVEC
|
||||
bool "Discard resetvec section and move bootpg section up"
|
||||
depends on MPC85xx
|
||||
|
|
|
|||
|
|
@ -18,8 +18,6 @@
|
|||
|
||||
/* IP endianness */
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_SFP_BE
|
||||
#define CONFIG_SYS_FSL_SEC_MON_BE
|
||||
|
||||
#if defined(CONFIG_ARCH_MPC8548)
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
|
||||
|
|
@ -35,7 +33,6 @@
|
|||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
/* P1011 is single core version of P1020 */
|
||||
#elif defined(CONFIG_ARCH_P1011)
|
||||
|
|
@ -150,7 +147,6 @@
|
|||
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
#elif defined(CONFIG_ARCH_BSC9132)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
|
|
@ -162,7 +158,6 @@
|
|||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
|
||||
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
|
||||
#define CONFIG_ESDHC_HC_BLK_ADDR
|
||||
|
||||
#elif defined(CONFIG_ARCH_T4240)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -200,32 +195,21 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
|
||||
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
|
||||
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
|
||||
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_MAPLE
|
||||
#define CONFIG_SYS_CPRI
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_SYS_CPRI_CLK 3
|
||||
#define CONFIG_SYS_ULB_CLK 4
|
||||
#define CONFIG_SYS_ETVPE_CLK 1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
#ifdef CONFIG_ARCH_B4860
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
|
|
@ -273,7 +257,6 @@
|
|||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
#elif defined(CONFIG_ARCH_T1024)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -300,7 +283,6 @@
|
|||
#define QE_MURAM_SIZE 0x6000UL
|
||||
#define MAX_QE_RISC 1
|
||||
#define QE_NUM_OF_SNUM 28
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
#elif defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
@ -310,7 +292,6 @@
|
|||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
|
|
@ -330,10 +311,8 @@
|
|||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_ISBC_VER 2
|
||||
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
|
||||
|
||||
#elif defined(CONFIG_ARCH_C29X)
|
||||
|
|
|
|||
|
|
@ -10,19 +10,12 @@
|
|||
#ifdef CONFIG_NXP_ESBC
|
||||
#if defined(CONFIG_FSL_CORENET)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
|
||||
#elif defined(CONFIG_TARGET_BSC9132QDS)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
|
||||
#elif defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
|
||||
#else
|
||||
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
|
||||
|
||||
#if defined(CONFIG_TARGET_B4860QDS) || \
|
||||
defined(CONFIG_TARGET_B4420QDS) || \
|
||||
defined(CONFIG_TARGET_T4240QDS) || \
|
||||
defined(CONFIG_TARGET_T2080QDS) || \
|
||||
#if defined(CONFIG_TARGET_T2080QDS) || \
|
||||
defined(CONFIG_TARGET_T2080RDB) || \
|
||||
defined(CONFIG_TARGET_T1042RDB) || \
|
||||
defined(CONFIG_TARGET_T1042D4RDB) || \
|
||||
|
|
@ -31,7 +24,6 @@
|
|||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_CPC_REINIT_F
|
||||
#endif
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
#undef CONFIG_SYS_INIT_L3_ADDR
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
|
||||
#endif
|
||||
|
|
@ -47,10 +39,6 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_KEY_REVOCATION
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_P3041) || \
|
||||
defined(CONFIG_ARCH_P4080) || \
|
||||
defined(CONFIG_ARCH_P5040) || \
|
||||
|
|
@ -80,55 +68,9 @@
|
|||
#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
|
||||
#define CONFIG_SPL_JR0_LIODN_S 454
|
||||
#define CONFIG_SPL_JR0_LIODN_NS 458
|
||||
/*
|
||||
* Define the key hash for U-Boot here if public/private key pair used to
|
||||
* sign U-boot are different from the SRK hash put in the fuse
|
||||
* Example of defining KEY_HASH is
|
||||
* #define CONFIG_SPL_UBOOT_KEY_HASH \
|
||||
* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
|
||||
* else leave it defined as NULL
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
|
||||
#endif /* ifdef CONFIG_SPL_BUILD */
|
||||
|
||||
#define CONFIG_FSL_SEC_MON
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/*
|
||||
* fsl_setenv_chain_of_trust() must be called from
|
||||
* board_late_init()
|
||||
*/
|
||||
|
||||
/* If Boot Script is not on NOR and is required to be copied on RAM */
|
||||
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
|
||||
#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
|
||||
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
|
||||
#define CONFIG_BS_HDR_SIZE 0x00002000
|
||||
#define CONFIG_BS_ADDR_RAM 0x00012000
|
||||
#define CONFIG_BS_ADDR_DEVICE 0x00802000
|
||||
#define CONFIG_BS_SIZE 0x00001000
|
||||
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
|
||||
#else
|
||||
|
||||
/* The bootscript header address is different for B4860 because the NOR
|
||||
* mapping is different on B4 due to reduced NOR size.
|
||||
*/
|
||||
#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
|
||||
#elif defined(CONFIG_FSL_CORENET)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
|
||||
#elif defined(CONFIG_TARGET_BSC9132QDS)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
|
||||
#elif defined(CONFIG_TARGET_C29XPCIE)
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
|
||||
#else
|
||||
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
|
||||
#endif
|
||||
|
||||
#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
|
||||
|
||||
#include <config_fsl_chain_trust.h>
|
||||
#endif /* #ifndef CONFIG_SPL_BUILD */
|
||||
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_rsb3720"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/advantech/imx8qm_rom7720_a1/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -18,6 +18,4 @@ config IMX8MN_BEACON_2GB_LPDDR
|
|||
config IMX_CONFIG
|
||||
default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
def_bool y
|
||||
select BSH_SMM_S2_DDR3L_256
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_IMX8MN_BSH_SMM_S2PRO
|
||||
|
|
@ -44,6 +42,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
def_bool y
|
||||
select BSH_SMM_S2_DDR3L_512
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,44 +1,3 @@
|
|||
if !ARCH_IMX8M && !ARCH_IMX8
|
||||
|
||||
config CHAIN_OF_TRUST
|
||||
depends on !FIT_SIGNATURE && SECURE_BOOT
|
||||
imply CMD_BLOB
|
||||
imply CMD_HASH if ARM
|
||||
select FSL_CAAM
|
||||
select SPL_BOARD_INIT if (ARM && SPL)
|
||||
select SHA_HW_ACCEL
|
||||
select SHA_PROG_HW_ACCEL
|
||||
select ENV_IS_NOWHERE
|
||||
select CMD_EXT4 if ARM
|
||||
select CMD_EXT4_WRITE if ARM
|
||||
bool
|
||||
default y
|
||||
|
||||
config CMD_ESBC_VALIDATE
|
||||
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
|
||||
default y if CHAIN_OF_TRUST
|
||||
help
|
||||
This option enables two commands used for secure booting:
|
||||
|
||||
esbc_validate - validate signature using RSA verification
|
||||
esbc_halt - put the core in spin loop (Secure Boot Only)
|
||||
|
||||
endif
|
||||
|
||||
config VOL_MONITOR_LTC3882_READ
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor read"
|
||||
help
|
||||
This option enables LTC3882 voltage monitor read
|
||||
functionality. It is used by common VID driver.
|
||||
|
||||
config VOL_MONITOR_LTC3882_SET
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor set"
|
||||
help
|
||||
This option enables LTC3882 voltage monitor set
|
||||
functionality. It is used by common VID driver.
|
||||
|
||||
config USB_TCPC
|
||||
bool "USB Typec port controller simple driver"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Virtual address range for PCI region maps */
|
||||
#define SYS_PCI_MAP_START 0x80000000
|
||||
#define SYS_PCI_MAP_END 0xe0000000
|
||||
|
||||
static void *get_fdt_virt(void)
|
||||
{
|
||||
if (gd->flags & GD_FLG_RELOC)
|
||||
|
|
@ -101,7 +105,7 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
|
|||
map_addr += size - 1;
|
||||
map_addr &= ~(size - 1);
|
||||
|
||||
if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
|
||||
if (map_addr + size >= SYS_PCI_MAP_END)
|
||||
return -1;
|
||||
|
||||
/* Map virtual memory for range */
|
||||
|
|
@ -137,7 +141,7 @@ int misc_init_r(void)
|
|||
pci_get_regions(dev, &io, &mem, &pre);
|
||||
|
||||
/* Start MMIO and PIO range maps above RAM */
|
||||
map_addr = CONFIG_SYS_PCI_MAP_START;
|
||||
map_addr = SYS_PCI_MAP_START;
|
||||
|
||||
/* Map MMIO range */
|
||||
ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,114 +0,0 @@
|
|||
config CHAIN_OF_TRUST
|
||||
depends on !FIT_SIGNATURE && NXP_ESBC
|
||||
imply CMD_BLOB
|
||||
imply CMD_HASH if ARM
|
||||
select FSL_CAAM
|
||||
select ARCH_MISC_INIT
|
||||
select SPL_BOARD_INIT if (ARM && SPL)
|
||||
select SPL_HASH if (ARM && SPL)
|
||||
select SHA_HW_ACCEL
|
||||
select SHA_PROG_HW_ACCEL
|
||||
select ENV_IS_NOWHERE
|
||||
select CMD_EXT4 if ARM
|
||||
select CMD_EXT4_WRITE if ARM
|
||||
bool
|
||||
default y
|
||||
|
||||
config CMD_ESBC_VALIDATE
|
||||
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
|
||||
default y if CHAIN_OF_TRUST
|
||||
help
|
||||
This option enables two commands used for secure booting:
|
||||
|
||||
esbc_validate - validate signature using RSA verification
|
||||
esbc_halt - put the core in spin loop (Secure Boot Only)
|
||||
|
||||
config DEEP_SLEEP
|
||||
bool "Enable SoC deep sleep feature"
|
||||
default y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
|
||||
help
|
||||
Indicates this SoC supports deep sleep feature. If deep sleep is
|
||||
supported, core will start to execute uboot when wakes up.
|
||||
|
||||
config FSL_USE_PCA9547_MUX
|
||||
bool "Enable PCA9547 I2C Mux on Freescale boards"
|
||||
help
|
||||
This option enables the PCA9547 I2C mux on Freescale boards.
|
||||
|
||||
config VID
|
||||
bool "Enable Freescale VID"
|
||||
depends on I2C || DM_I2C
|
||||
help
|
||||
This option enables setting core voltage based on individual
|
||||
values saved in SoC fuses.
|
||||
|
||||
config SPL_VID
|
||||
bool "Enable Freescale VID in SPL"
|
||||
depends on I2C || DM_I2C
|
||||
help
|
||||
This option enables setting core voltage based on individual
|
||||
values saved in SoC fuses, in SPL.
|
||||
|
||||
if VID || SPL_VID
|
||||
|
||||
config VID_FLS_ENV
|
||||
string "Environment variable for overriding VDD"
|
||||
help
|
||||
This option allows for specifying the environment variable
|
||||
to check to override VDD information.
|
||||
|
||||
config VOL_MONITOR_INA220
|
||||
bool "Enable the INA220 voltage monitor read"
|
||||
help
|
||||
This option enables INA220 voltage monitor read
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_IR36021_READ
|
||||
bool "Enable the IR36021 voltage monitor read"
|
||||
help
|
||||
This option enables IR36021 voltage monitor read
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_IR36021_SET
|
||||
bool "Enable the IR36021 voltage monitor set"
|
||||
help
|
||||
This option enables IR36021 voltage monitor set
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_LTC3882_READ
|
||||
bool "Enable the LTC3882 voltage monitor read"
|
||||
help
|
||||
This option enables LTC3882 voltage monitor read
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_LTC3882_SET
|
||||
bool "Enable the LTC3882 voltage monitor set"
|
||||
help
|
||||
This option enables LTC3882 voltage monitor set
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_ISL68233_READ
|
||||
bool "Enable the ISL68233 voltage monitor read"
|
||||
help
|
||||
This option enables ISL68233 voltage monitor read
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
config VOL_MONITOR_ISL68233_SET
|
||||
bool "Enable the ISL68233 voltage monitor set"
|
||||
help
|
||||
This option enables ISL68233 voltage monitor set
|
||||
functionality. It is used by the common VID driver.
|
||||
|
||||
endif
|
||||
|
||||
config FSL_QIXIS
|
||||
bool "Enable QIXIS support"
|
||||
|
||||
config QIXIS_I2C_ACCESS
|
||||
bool "Access to QIXIS is over i2c"
|
||||
depends on FSL_QIXIS
|
||||
default y
|
||||
|
||||
config HAS_FSL_DR_USB
|
||||
def_bool y
|
||||
depends on USB_EHCI_HCD && PPC
|
||||
|
|
@ -12,6 +12,7 @@
|
|||
#include <fsl_sfp.h>
|
||||
#include <log.h>
|
||||
#include <dm/root.h>
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
|
||||
#include <spl.h>
|
||||
|
|
@ -76,14 +77,14 @@ int fsl_setenv_chain_of_trust(void)
|
|||
|
||||
/* If Boot mode is Secure, set the environment variables
|
||||
* bootdelay = 0 (To disable Boot Prompt)
|
||||
* bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
|
||||
* bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script)
|
||||
*/
|
||||
env_set("bootdelay", "-2");
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
env_set("secureboot", "y");
|
||||
#else
|
||||
env_set("bootcmd", CONFIG_CHAIN_BOOT_CMD);
|
||||
env_set("bootcmd", CHAIN_BOOT_CMD);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -871,7 +871,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
|
|||
int ret, i, hash_cmd = 0;
|
||||
u32 srk_hash[8];
|
||||
|
||||
if (arg_hash_str != NULL) {
|
||||
if (strlen(arg_hash_str) != 0) {
|
||||
const char *cp = arg_hash_str;
|
||||
int i = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -166,4 +166,25 @@ defined(CONFIG_TARGET_LX2160ARDB)
|
|||
#define QIXIS_ESDHC_NO_ADAPTER 0x7
|
||||
#endif
|
||||
|
||||
/*
|
||||
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
||||
*/
|
||||
static inline u8 qixis_esdhc_detect_quirk(void)
|
||||
{
|
||||
/*
|
||||
* SDHC1 Card ID:
|
||||
* Specifies the type of card installed in the SDHC1 adapter slot.
|
||||
* 000= (reserved)
|
||||
* 001= eMMC V4.5 adapter is installed.
|
||||
* 010= SD/MMC 3.3V adapter is installed.
|
||||
* 011= eMMC V4.4 adapter is installed.
|
||||
* 100= eMMC V5.0 adapter is installed.
|
||||
* 101= MMC card/Legacy (3.3V) adapter is installed.
|
||||
* 110= SDCard V2/V3 adapter installed.
|
||||
* 111= no adapter is installed.
|
||||
*/
|
||||
return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
|
||||
QIXIS_ESDHC_NO_ADAPTER);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,8 +9,6 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "P3041DS"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_P4080DS
|
||||
|
|
@ -24,8 +22,6 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "P4080DS"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_P5040DS
|
||||
|
|
@ -39,6 +35,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "P5040DS"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,4 @@ config IMX8MN_LOW_DRIVE_MODE
|
|||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/freescale/imx8qm_mek/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/freescale/imx8qxp_mek/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8ulp_evk"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -89,7 +89,3 @@ config SYS_LS_PFE_ESBC_LENGTH
|
|||
hex "length of PFE Firmware HDR"
|
||||
default 0xc00
|
||||
endif
|
||||
|
||||
if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -77,7 +77,4 @@ config PFE_SGMII_2500_PHY2_ADDR
|
|||
|
||||
endif
|
||||
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -63,8 +63,6 @@ config PFE_EMAC2_PHY_ADDR
|
|||
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_LS1012A2G5RDB
|
||||
|
|
@ -119,6 +117,4 @@ config PFE_EMAC2_PHY_ADDR
|
|||
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls1021aiot"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls1021aqds"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -13,6 +13,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls1021atsn"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls1021atwr"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -32,8 +32,6 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_LS1028ARDB
|
||||
|
|
@ -58,6 +56,4 @@ config SYS_TEXT_BASE
|
|||
default 0x82000000 if TFABOOT
|
||||
default 0x20100000
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -27,6 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -13,5 +13,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls1046afrwy"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -28,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -27,5 +27,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
||||
if TARGET_LS1088ARDB
|
||||
|
|
@ -57,5 +56,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -29,6 +29,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "ls2080ardb"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
if FSL_LS_PPA
|
||||
config SYS_LS_PPA_FW_ADDR
|
||||
hex "PPA Firmware Addr"
|
||||
|
|
@ -30,6 +28,4 @@ config SYS_LS_PPA_ESBC_ADDR
|
|||
endif
|
||||
endif
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "lx2160ardb"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
||||
if TARGET_LX2160AQDS
|
||||
|
|
@ -29,7 +28,6 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "lx2160aqds"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
||||
if TARGET_LX2162AQDS
|
||||
|
|
@ -46,5 +44,4 @@ config SYS_SOC
|
|||
config SYS_CONFIG_NAME
|
||||
default "lx2162aqds"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -356,27 +356,6 @@ int checkboard(void)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
|
||||
/*
|
||||
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
||||
*/
|
||||
u8 qixis_esdhc_detect_quirk(void)
|
||||
{
|
||||
/*
|
||||
* SDHC1 Card ID:
|
||||
* Specifies the type of card installed in the SDHC1 adapter slot.
|
||||
* 000= (reserved)
|
||||
* 001= eMMC V4.5 adapter is installed.
|
||||
* 010= SD/MMC 3.3V adapter is installed.
|
||||
* 011= eMMC V4.4 adapter is installed.
|
||||
* 100= eMMC V5.0 adapter is installed.
|
||||
* 101= MMC card/Legacy (3.3V) adapter is installed.
|
||||
* 110= SDCard V2/V3 adapter installed.
|
||||
* 111= no adapter is installed.
|
||||
*/
|
||||
return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
|
||||
QIXIS_ESDHC_NO_ADAPTER);
|
||||
}
|
||||
|
||||
static void esdhc_adapter_card_ident(void)
|
||||
{
|
||||
u8 card_id, val;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,8 @@
|
|||
if TARGET_MPC8548CDS
|
||||
|
||||
config PCI1
|
||||
def_bool y
|
||||
|
||||
config SYS_BOARD
|
||||
default "mpc8548cds"
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "P1010RDB"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "p1_p2_rdb_pc"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "P2041RDB"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "T102xRDB"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "T104xRDB"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config SRIO_PCIE_BOOT_SLAVE
|
||||
bool "Boot as a SRIO PCIe slave device"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config T2080RDB_REV_D
|
||||
bool "Support for T2080RDB revisions D and up"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "T4240RDB"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ config S5P4418_ONEWIRE
|
|||
|
||||
config PWM_NX
|
||||
bool "PWM"
|
||||
select PWM_S5P
|
||||
help
|
||||
This enables LCD-Backlight control via PWM.
|
||||
endchoice
|
||||
|
|
|
|||
|
|
@ -59,7 +59,8 @@ int checkboard (void)
|
|||
f = get_board_sys_clk();
|
||||
} else {
|
||||
src = "PCI_CLK";
|
||||
f = CONFIG_PCI_CLK_FREQ;
|
||||
/* PCI is clocked by the external source at 33 MHz */
|
||||
f = 33000000;
|
||||
}
|
||||
printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -3,6 +3,9 @@ if TARGET_STMARK2
|
|||
config CF_SBF
|
||||
def_bool y
|
||||
|
||||
config EXTRA_CLOCK
|
||||
def_bool y
|
||||
|
||||
config SYS_INPUT_CLKSRC
|
||||
hex
|
||||
default 30000000
|
||||
|
|
|
|||
|
|
@ -12,6 +12,4 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/variscite/imx8mn_var_som/imximage-8mn-ddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
13
boot/Kconfig
13
boot/Kconfig
|
|
@ -575,6 +575,19 @@ config SPIFLASH
|
|||
|
||||
endchoice
|
||||
|
||||
config FSL_FIXED_MMC_LOCATION
|
||||
bool "PBL MMC is at a fixed location"
|
||||
depends on SDCARD && !RAMBOOT_PBL
|
||||
|
||||
config ESDHC_HC_BLK_ADDR
|
||||
def_bool y
|
||||
depends on FSL_FIXED_MMC_LOCATION && (ARCH_BSC9131 || ARCH_BSC9132 || ARCH_P1010)
|
||||
help
|
||||
In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
|
||||
code length of these soc specify the memory address in block address
|
||||
format. Block length is fixed to 512 bytes as per the SD High
|
||||
Capacity specification.
|
||||
|
||||
config SYS_FSL_PBL_PBI
|
||||
string "PBI(pre-boot instructions) commands for the PBL image"
|
||||
depends on RAMBOOT_PBL
|
||||
|
|
|
|||
|
|
@ -1298,6 +1298,10 @@ config CMD_ONENAND
|
|||
and erasing blocks. It allso provides a way to show and change
|
||||
bad blocks, and test the device.
|
||||
|
||||
config USE_ONENAND_BOARD_INIT
|
||||
bool "Call onenand_board_init() in the onenand command"
|
||||
depends on CMD_ONENAND
|
||||
|
||||
config CMD_OSD
|
||||
bool "osd"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -400,13 +400,9 @@ static int reserve_video(void)
|
|||
((unsigned long)gd->relocaddr - addr) >> 10, addr);
|
||||
gd->relocaddr = addr;
|
||||
#elif defined(CONFIG_LCD)
|
||||
# ifdef CONFIG_FB_ADDR
|
||||
gd->fb_base = CONFIG_FB_ADDR;
|
||||
# else
|
||||
/* reserve memory for LCD display (always full pages) */
|
||||
gd->relocaddr = lcd_setmem(gd->relocaddr);
|
||||
gd->fb_base = gd->relocaddr;
|
||||
# endif /* CONFIG_FB_ADDR */
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8548CDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8548CDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
|
||||
|
|
|
|||
|
|
@ -10,7 +10,9 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8548CDS=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_TARGET_MPC8548CDS_LEGACY=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -79,7 +82,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_TPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -8,12 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -46,7 +50,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_COMMON_INIT_DDR=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
|
|
|
|||
|
|
@ -13,13 +13,17 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -68,7 +72,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -71,7 +74,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -78,7 +81,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_TPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -8,11 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -45,7 +49,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_COMMON_INIT_DDR=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
|
|
|
|||
|
|
@ -13,12 +13,16 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -67,7 +71,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PA=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -70,7 +73,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -80,7 +83,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_TPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -8,12 +8,16 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -47,7 +51,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_COMMON_INIT_DDR=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
|
|
|
|||
|
|
@ -13,13 +13,17 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -69,7 +73,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -72,7 +75,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -79,7 +82,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_TPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -8,11 +8,15 @@ CONFIG_ENV_ADDR=0xEFF20000
|
|||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -46,7 +50,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_COMMON_INIT_DDR=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
|
|
|
|||
|
|
@ -13,12 +13,16 @@ CONFIG_SPL_DRIVERS_MISC=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs ramdisk_size=$ramdisk_size;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
|
@ -68,7 +72,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|||
CONFIG_SPL_SPI=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_P1010RDB_PB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -71,7 +74,9 @@ CONFIG_FSL_SATA_V2=y
|
|||
CONFIG_SYS_SATA_MAX_DEVICE=2
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SPL_COMMON_INIT_DDR=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -77,7 +80,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xFF800C21
|
||||
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
|
||||
|
|
|
|||
|
|
@ -13,8 +13,11 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -22,6 +25,7 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -67,7 +71,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -70,7 +73,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -9,13 +9,17 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -46,7 +50,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -76,7 +79,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xFF800C21
|
||||
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
|
||||
|
|
|
|||
|
|
@ -13,14 +13,18 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -66,7 +70,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -69,7 +72,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -9,12 +9,16 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PC=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -45,7 +49,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEF001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PD=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -79,7 +82,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=2
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xFF800C21
|
||||
CONFIG_SYS_OR0_PRELIM=0xFFFF8796
|
||||
|
|
|
|||
|
|
@ -13,14 +13,18 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PD=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SPL_SYS_MONITOR_BASE=0xF8F80000
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -69,7 +73,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=2
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEC001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -15,8 +15,11 @@ CONFIG_SPL_SPI=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PD=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -72,7 +75,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=2
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEC001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -9,12 +9,16 @@ CONFIG_MPC85xx=y
|
|||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P1020RDB_PD=y
|
||||
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_FSL_FIXED_MMC_LOCATION=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
|
||||
|
|
@ -48,7 +52,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=2
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xEC001001
|
||||
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
|
||||
|
|
|
|||
|
|
@ -14,8 +14,11 @@ CONFIG_SPL=y
|
|||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_P2020RDB=y
|
||||
CONFIG_ENABLE_36BIT_PHYS=y
|
||||
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
|
||||
CONFIG_PCIE1=y
|
||||
CONFIG_PCIE2=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -81,7 +84,9 @@ CONFIG_ETHPRIME="eTSEC1"
|
|||
CONFIG_DM=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_DDR_CLK_FREQ=66666666
|
||||
CONFIG_SYS_SPD_BUS_NUM=1
|
||||
CONFIG_CHIP_SELECTS_PER_CTRL=1
|
||||
CONFIG_SYS_DDR_RAW_TIMING=y
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0xFF800C21
|
||||
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue