Commit graph

14 commits

Author SHA1 Message Date
Chin Liang See
0db1ac47ee arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:08 +02:00
Marek Vasut
dbd6fcfbe2 arm: socfpga: Drop the board boilerplate
Drop all the common board code, since it is not completely useless.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut
70311e69fa arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:50 +01:00
Marek Vasut
6b9cdb716f arm: socfpga: arria5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:49 +01:00
Marek Vasut
5d5716eebc usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.

The rename is done automatically:
	$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
		`git grep "s3c_udc\.h" | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:41 +01:00
Marek Vasut
a4bb9b3636 usb: s3c-otg: Rename s3c_udc_probe() function
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.

The rename is done automatically:
	$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
		`git grep s3c_udc_probe | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Marek Vasut
c0982871df usb: s3c-otg: Rename struct s3c_plat_otg_data
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
	$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
		`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
2015-12-17 21:54:40 +01:00
Dinh Nguyen
4348f36bbb arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-23 03:55:28 +02:00
Marek Vasut
29aa439759 arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
Marek Vasut
d418301167 arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK
Repair the maintainer entries so they match the current state of code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
cc9429a556 arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f6badb0d89 arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
c68eea0492 arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f089240128 arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00