Add clock, phy and other configuration, it is convenient to support
new controller. Here a short summary of the changes:
- Add mmc_of_parse to parse dts config.
- Remove OF_PLATDATA related code.
- Reorder header inclusion.
- Add phy ops.
- add ops set_ios_post to modify the parameters of phy when the
clock changes.
- Add execute tuning api for hs200 tuning.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add iMX8ULP DDR initialization driver which loads the DDR timing
parameters and executes the training procedure.
When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode
to do DDR init
Signed-off-by: Ye Li <ye.li@nxp.com>
This driver uses FSB to read some fuses, but not support program fuse.
It only works in SPL (secure mode), u-boot needs traps to ATF to
read them.
Some fuses can read from S400 API and others are from FSB.
Also support program some fuses via S400 API
Signed-off-by: Ye Li <ye.li@nxp.com>
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
According to latest S400 API doc, the the success indicate value is
changed to 0xd6. So update the driver codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
At present it is possible to call uclass_get() before driver model is
inited. In fact this happens on x86 boards which use Intel FSPv1, since
mrccache_get_region() tries to get the SPI flash device very early
during init.
This has always been undefined behaviour. Previously it generally worked,
i.e. returned an error code without crashing, because gd->uclass_root_s
is zeroed and the uclass can be added despite driver model not being
ready, due to the way lists are implemented. With the change to use a
gd->uclass_root pointer, this no-longer works. For example, it causes a
hang on minnowmax.
Fix this by adding a check that driver model is ready when uclass_get() is
called. This function is called in the process of locating any device, so
it is a good place to add the check.
This fixes booting on minnowmax.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 8a715530bb ("dm: core: Allow the uclass list to move")
Migrate the dm_warn function to log macro with
LOGC_DM category and LOGL_WARNING level.
This macro allows filtering with log command and allows
output on all log backend.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that DM_PCI is always enabled, check on CONFIG_PCI instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for non-PCI users of this code, reword]
Signed-off-by: Tom Rini <trini@konsulko.com>
The DT bindings of "jedec,spi-nor" [1] defines "m25p,fast-read" property
to indicate that "fast read" opcode can be used to read data from the
chip instead of the usual "read" opcode.
If this property is not present in DT, mask out fast read in
spi_nor_init_params(). This change mirrors the same logic in
spi_nor_info_init_params() in drivers/mtd/spi-nor/core.c in
the Linux kernel v5.14-rc3.
[1] Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml in the kernel tree
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's
hwcaps, and only looks to the controller on what can be supported.
The flash's hwcaps needs to be AND'ed before checking.
Fixes: 71025f013c ("mtd: spi-nor-core: Rework hwcaps selection")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
When slave drivers don't set the max_read_size, the spi-mem should
directly use data.nbytes and not limit to any size. But current
logic will limit to the max_write_size.
This commit mirrors the same changes in the dm version done in
commit 535b1fdb8e ("spi: spi-mem: Fix read data size issue").
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA
smart gateway.
Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.
Add a proper comment to simple_strtoul() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.
This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit 43c145b8b3 ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.
ICH controller can only transfer a small number of bytes at once.
Before commit 43c145b8b3, the logic happens to make sure data.nbytes
is limited to slave->max_write_size but after commit 43c145b8b3
data.nbytes is no longer limited because slave->max_read_size is not
initialized with a valid number.
Fixes: 43c145b8b3 ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Hitachi tx18d42vm LCD panel driver is really just initialising the
device, using bitbanged SPI, during operation there is nothing to do.
This makes the driver self contained, so drop the bogus dependency on
the legacy CONFIG_VIDEO.
This avoids the warning when building Chuwi_V7_CW0825_defconfig, since
we switched to DM_VIDEO recently.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The U-Boot port for ST-Ericsson Ux500 is currently only used on the
"stemmy" board, where U-Boot runs after firmware that already sets up
a boot splash screen. This means that the display is already on
and we can just continue using it for U-Boot.
Add a simple driver that simplifies this by reading the display
configuration (e.g. screen size, bpp) from the hardware registers.
It also checks the configured "source synchronization" - for some
displays (usually DSI command mode displays) we need to explicitly
trigger a software sync. This is done through the video_sync()
callback that triggers the sync and wait for completion.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
It is fairly easy to handle this case and it makes the emulator more
useful, since PCRs are commonly extended several times.
Add support for this, using U-Boot's sha256 support.
For now sandbox only supports a single PCR, but that is enough for the
tests that currently exist.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is the number of PCRs, so the current check is off by one. Also the
map itself should not be checked, just the resulting pcr_index, to avoid
confusing people who read the code.
Fix these problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the tpm2 emulator does not support storing the device state.
Add this so we can handle the normal vboot flow through the sandbox
executables (VPL->SPL etc.) with the TPM contents staying in place.
Note: sandbox has not yet been converted to use livetree for the state
information, since livetree does not yet support writing to the tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add checking as to whether the current TPM state is valid, so we can
implement reading/writing the state.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function current handles the kernel case incorrectly. Fix it, and
use the shorter TPM_HDR_LEN while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for this command, moving away from the previous approach of
hard-coding the initial data in the driver, now that the kernel-space data
has to be set up by the higher-level vboot code.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this code assumes that the TPM data has been read but this may
not be the case. Refactor the code to use a separate pointer so we know
the current state of the data.
Add error checking for the data size.
Signed-off-by: Simon Glass <sjg@chromium.org>
