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mmc: rockchip_sdhci: add phy and clock config for rk3399
Add clock, phy and other configuration, it is convenient to support new controller. Here a short summary of the changes: - Add mmc_of_parse to parse dts config. - Remove OF_PLATDATA related code. - Reorder header inclusion. - Add phy ops. - add ops set_ios_post to modify the parameters of phy when the clock changes. - Add execute tuning api for hs200 tuning. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Yifeng Zhao
Kever Yang
parent
d2a74ec91b
commit
ac804143cf
1 changed files with 280 additions and 39 deletions
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@ -6,90 +6,322 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/ofnode.h>
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#include <dt-structs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/libfdt.h>
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#include <linux/iopoll.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include "mmc_private.h"
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#include <sdhci.h>
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#include <clk.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/hardware.h>
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/* 400KHz is max freq for card ID etc. Use that as min */
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#define EMMC_MIN_FREQ 400000
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#define KHz (1000)
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#define MHz (1000 * KHz)
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#define SDHCI_TUNING_LOOP_COUNT 40
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_FREQSEL_200M 0x0
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#define PHYCTRL_FREQSEL_50M 0x1
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#define PHYCTRL_FREQSEL_100M 0x2
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#define PHYCTRL_FREQSEL_150M 0x3
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#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \
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((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
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PHYCTRL_DLLRDY_DONE)
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struct rockchip_sdhc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_sdhc {
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struct sdhci_host host;
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void *base;
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struct rockchip_emmc_phy {
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u32 emmcphy_con[7];
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u32 reserved;
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u32 emmcphy_status;
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};
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static int arasan_sdhci_probe(struct udevice *dev)
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struct rockchip_sdhc {
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struct sdhci_host host;
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struct udevice *dev;
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void *base;
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struct rockchip_emmc_phy *phy;
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struct clk emmc_clk;
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};
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struct sdhci_data {
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int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
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int (*emmc_phy_init)(struct udevice *dev);
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int (*get_phy)(struct udevice *dev);
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};
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static int rk3399_emmc_phy_init(struct udevice *dev)
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{
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return 0;
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}
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static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
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{
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u32 caldone, dllrdy, freqsel;
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writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(3);
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writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
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/*
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* According to the user manual, it asks driver to
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* wait 5us for calpad busy trimming. But it seems that
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* 5us of caldone isn't enough for all cases.
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*/
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udelay(500);
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caldone = readl(&phy->emmcphy_status);
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caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
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if (caldone != PHYCTRL_CALDONE_DONE) {
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printf("%s: caldone timeout.\n", __func__);
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return;
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}
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/* Set the frequency of the DLL operation */
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if (clock < 75 * MHz)
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freqsel = PHYCTRL_FREQSEL_50M;
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else if (clock < 125 * MHz)
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freqsel = PHYCTRL_FREQSEL_100M;
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else if (clock < 175 * MHz)
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freqsel = PHYCTRL_FREQSEL_150M;
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else
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freqsel = PHYCTRL_FREQSEL_200M;
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/* Set the frequency of the DLL operation */
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writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
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read_poll_timeout(readl, &phy->emmcphy_status, dllrdy,
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PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000);
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}
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static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
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{
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writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
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}
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static int rk3399_emmc_get_phy(struct udevice *dev)
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{
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struct rockchip_sdhc *priv = dev_get_priv(dev);
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ofnode phy_node;
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void *grf_base;
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u32 grf_phy_offset, phandle;
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phandle = dev_read_u32_default(dev, "phys", 0);
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phy_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(phy_node)) {
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debug("Not found emmc phy device\n");
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return -ENODEV;
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}
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grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (grf_base < 0) {
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printf("%s Get syscon grf failed", __func__);
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return -ENODEV;
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}
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grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
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priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
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return 0;
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}
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static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
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if (cycle_phy)
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rk3399_emmc_phy_power_off(priv->phy);
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sdhci_set_clock(host->mmc, clock);
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if (cycle_phy)
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rk3399_emmc_phy_power_on(priv->phy, clock);
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return 0;
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}
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static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
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struct mmc *mmc = host->mmc;
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uint clock = mmc->tran_speed;
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u32 reg;
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if (!clock)
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clock = mmc->clock;
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if (data->emmc_set_clock)
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data->emmc_set_clock(host, clock);
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if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
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reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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reg &= ~SDHCI_CTRL_UHS_MASK;
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reg |= SDHCI_CTRL_HS400;
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sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
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} else {
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sdhci_set_uhs_timing(host);
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}
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return 0;
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}
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static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct sdhci_host *host = dev_get_priv(mmc->dev);
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char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
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struct mmc_cmd cmd;
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u32 ctrl, blk_size;
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int ret = 0;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
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blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
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blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
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sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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cmd.cmdidx = opcode;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = 0;
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do {
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if (tuning_loop_counter-- == 0)
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break;
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mmc_send_cmd(mmc, &cmd, NULL);
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if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
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/*
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* For tuning command, do not do busy loop. As tuning
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* is happening (CLK-DATA latching for setup/hold time
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* requirements), give time to complete
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*/
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udelay(1);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
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printf("%s:Tuning failed\n", __func__);
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ret = -EIO;
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}
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if (tuning_loop_counter < 0) {
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ctrl &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
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}
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/* Enable only interrupts served by the SD controller */
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
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/* Mask all sdhci interrupt sources */
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
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return ret;
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}
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static struct sdhci_ops rockchip_sdhci_ops = {
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.set_ios_post = rockchip_sdhci_set_ios_post,
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.platform_execute_tuning = &rockchip_sdhci_execute_tuning,
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};
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static int rockchip_sdhci_probe(struct udevice *dev)
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{
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struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
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struct rockchip_sdhc *prv = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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struct sdhci_host *host = &prv->host;
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int max_frequency, ret;
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struct clk clk;
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int ret;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
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host->name = dev->name;
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host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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max_frequency = dtplat->max_frequency;
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ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk);
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#else
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max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
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host->max_clk = cfg->f_max;
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ret = clk_get_by_index(dev, 0, &clk);
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#endif
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if (!ret) {
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ret = clk_set_rate(&clk, max_frequency);
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ret = clk_set_rate(&clk, host->max_clk);
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if (IS_ERR_VALUE(ret))
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printf("%s clk set rate fail!\n", __func__);
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} else {
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printf("%s fail to get clk\n", __func__);
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}
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prv->emmc_clk = clk;
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prv->dev = dev;
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if (data->get_phy) {
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ret = data->get_phy(dev);
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if (ret)
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return ret;
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}
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if (data->emmc_phy_init) {
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ret = data->emmc_phy_init(dev);
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if (ret)
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return ret;
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}
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host->ops = &rockchip_sdhci_ops;
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
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host->max_clk = max_frequency;
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/*
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* The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
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* doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
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* check for other bus-width values.
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*/
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if (host->bus_width == 8)
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host->host_caps |= MMC_MODE_8BIT;
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host->mmc = &plat->mmc;
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host->mmc->priv = &prv->host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
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ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
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if (ret)
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return ret;
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return sdhci_probe(dev);
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}
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static int arasan_sdhci_of_to_plat(struct udevice *dev)
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static int rockchip_sdhci_of_to_plat(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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int ret;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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#endif
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ret = mmc_of_parse(dev, cfg);
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if (ret)
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return ret;
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return 0;
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}
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@ -101,19 +333,28 @@ static int rockchip_sdhci_bind(struct udevice *dev)
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-5.1" },
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static const struct sdhci_data rk3399_data = {
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.emmc_set_clock = rk3399_sdhci_emmc_set_clock,
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.get_phy = rk3399_emmc_get_phy,
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.emmc_phy_init = rk3399_emmc_phy_init,
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};
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static const struct udevice_id sdhci_ids[] = {
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{
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.compatible = "arasan,sdhci-5.1",
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.data = (ulong)&rk3399_data,
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},
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{ }
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};
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U_BOOT_DRIVER(arasan_sdhci_drv) = {
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.name = "rockchip_rk3399_sdhci_5_1",
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.name = "rockchip_sdhci_5_1",
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.id = UCLASS_MMC,
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.of_match = arasan_sdhci_ids,
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.of_to_plat = arasan_sdhci_of_to_plat,
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.of_match = sdhci_ids,
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.of_to_plat = rockchip_sdhci_of_to_plat,
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.ops = &sdhci_ops,
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.bind = rockchip_sdhci_bind,
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.probe = arasan_sdhci_probe,
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.probe = rockchip_sdhci_probe,
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.priv_auto = sizeof(struct rockchip_sdhc),
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.plat_auto = sizeof(struct rockchip_sdhc_plat),
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};
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