Commit graph

12205 commits

Author SHA1 Message Date
Gustavo A. R. Silva
eacccbda43 usb: xhci: Fix bool initialization in xhci_bulk_tx
Bool initializations should use true and false.

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
2018-01-25 20:59:16 +01:00
Goldschmidt Simon
92962b3caf ddr: altera: silence PHY calibration unless in debug mode
This driver has been using printf() including filename since it was
added. Convert to using debug() instead.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-01-25 09:59:37 +01:00
Marek Vasut
34e93605ae pinctrl: rmobile: Import R8A7794 E2 PFC tables
Import PFC tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:23 +01:00
Marek Vasut
ab2d09b4be pinctrl: rmobile: Import R8A7792 V2H PFC tables
Import PFC tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:23 +01:00
Marek Vasut
427c75df5a pinctrl: rmobile: Import R8A7791/R8A7793 M2 PFC tables
Import PFC tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:23 +01:00
Marek Vasut
7547ad4ca0 pinctrl: rmobile: Import R8A7790 H2 PFC tables
Import PFC tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
19b1a8b7a7 clk: renesas: Import R8A7794 E2 clock tables
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
ce43893d4d clk: renesas: Import R8A7792 V2H clock tables
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
67dbebe203 clk: renesas: Import R8A7791/R8A7793 M2 clock tables
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
75a5096da4 clk: renesas: Import R8A7790 H2 clock tables
Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
dedb60fb5b clk: renesas: Add Gen2 clock core
Add common clock code for Renesas RCar Gen2 platforms.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
28b8f225b4 clk: renesas: Add DIV6P1 clock type
Add macros for the DIV6P1 clock type, which is used on Gen2
and optionally also on Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
d26286715f clk: renesas: Split out code shared between Gen2 and Gen3
Pull code which is common for RCar Gen2 and RCar Gen3 into
separate source file. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
65f1bbf678 clk: renesas: Make clock tables Kconfig configurable
Add Kconfig entries for each SoC clock table, so they can be
compiled in or out at build time. This can reduce the size of
the binary if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
ff50b323b3 clk: renesas: Split SMSTPCR and RMSTPCR tables
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
58f1788f47 clk: renesas: Pull Gen3 specific bits into separate header
Extract the macros specific to Gen3 clock into a separate header.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
7c88556323 clk: renesas: Make PLL configurations per-SoC
Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Marek Vasut
f11c9679ab clk: renesas: Make clk_ids per-driver
Not all drivers use the same IDs, so make those IDs per-driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Marek Vasut
f77b5a4cd1 clk: renesas: Split RCar Gen3 driver
Split the massive driver into smaller per-SoC drivers and pull the
common code into a separate file. This would allow configuring out
unnecessary clock drivers once the Kconfig changes are in and also
allow adding more clock tables easily.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Chris Brandt
8591ac8b16 serial: sh: Add support for R7S72100 (RZ/A1)
Add support for RZ/A1 series SoCs.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
2018-01-24 23:27:21 +01:00
Marek Vasut
a6e25b2e12 serial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2
Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Marek Vasut
c493756ab4 serial: sh: Replace fdtdec_get_addr() with devfdt_get_addr()
Replace fdtdec_get_addr() with devfdt_get_addr() as the later one is
the current recommended practice.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Tom Rini
fb4413295c Merge git://git.denx.de/u-boot-mmc 2018-01-24 11:28:44 -05:00
Jun Nie
2f516e4aa2 mmc: Poll for broken card detection case
Poll for broken card detection case instead of return
no card detected.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
2018-01-24 16:12:03 +09:00
Jaehoon Chung
c0fafe64a5 mmc: fix to assign to correct clock value when clock is enabling
When clock is enabling, it's assigned to 0 as mmc->clock.
Then it can't initialize any card.
Fix to assign to correct clock value as mmc->cfg->f_min or f_max.

Fixes: 9546eb92cb ("mmc: fix the wrong disabling clock")
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2018-01-24 16:08:27 +09:00
Jaehoon Chung
173f023f46 power: pmic: s2mps11: probe the regulator driver
Add the probe function to support the s2mps11 regulator driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-24 16:07:35 +09:00
Jaehoon Chung
60599ea6cd power: regulator: s2mps11: add a regulator driver for s2mps11
exynos5422 has the s2mps11 PMIC.
s2mps11 pmic has the 10-BUCK and 38-LDO regulators.
Each IP and devices in exynos5422 can be controlled by each regulators.
This patch is support for s2mps11 regulator driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-24 16:07:19 +09:00
Vignesh R
aaa21d3ffc spi: cadence_qspi_apb: Make flash writes 32 bit aligned
Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Vignesh R
a743e2ba38 Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"
This reverts commit 57897c13de.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Goldschmidt Simon
948ad4f075 Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
This reverts commit b63b46313e.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Jason Rush
15a70a5da3 spi: cadence_spi: Sync DT bindings with Linux
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-01-24 12:07:50 +05:30
Chris Packham
df16881cea spi: kirkwood_spi: implement workaround for FE-9144572
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz.  However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.

Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:08 +05:30
Mario Six
36890ff0d0 sf_probe: Merge spi_flash_probe_tail into spi_flash_probe
spi_flash_probe_tail is now only called from spi_flash_probe, hence we
can merge its body into spi_flash_probe.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:08 +05:30
Mario Six
24fc1ec2ee spi: spi-uclass: Fix style violations
Remove a superfluous newline, and reduce the scope of a variable.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:08 +05:30
Mario Six
a3e32c5038 spi: sf_probe: Fix style violations
Fix two indention-related style violations.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:08 +05:30
Mario Six
184fa1c8da spi: Remove spi_setup_slave_fdt
A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.

This patch removes the function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:07 +05:30
Mario Six
74ea6e82f8 spi: Remove spi_flash_probe_fdt
Commit ba45756 ("dm: x86: spi: Convert ICH SPI driver to driver model")
removed the last usage of the spi_flash_probe_fdt function, rendering it
obsolete.

This patch removes the function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:07 +05:30
Mario Six
c5b88f29ba spi: Remove obsolete spi_base_setup_slave_fdt
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT
node") added a helper function spi_base_setup_slave_fdt to to set up a
SPI slave from a given FDT blob. The only user was the exynos SPI
driver.

But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed
the use of this function, hence rendering it obsolete.

Remove this function, as well as the CONFIG_OF_SPI option, which guarded
only this function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:07 +05:30
Mario Six
547bcc3d18 spi: Fix style violation and improve code
This patch fixes a printf specifier style violation, reduces the scope
of a variable, and turns a void pointer that is used with pointer
arithmetic into a u8 pointer.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:07 +05:30
Álvaro Fernández Rojas
29cc4368ad dm: spi: add BCM63xx HSSPI driver
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:06 +05:30
Álvaro Fernández Rojas
5ac07d2969 dm: spi: add BCM63xx SPI driver
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Álvaro Fernández Rojas
6c94bd12c4 drivers: spi: consider command bytes when sending transfers
Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Álvaro Fernández Rojas
8af74edc30 drivers: spi: allow limiting reads
For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Tom Rini
1612128018 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-01-23 21:48:53 -05:00
Breno Lima
d7af2baa49 crypto/fsl: Fix HW accelerated hash commands
The hash command function were not flushing the dcache before passing data
to CAAM/DMA and not invalidating the dcache when getting data back.

Due the data cache incoherency, HW accelerated hash commands used to fail
with CAAM errors like "Invalid KEY Command".

Check if pbuf and pout buffers are properly aligned to the cache line size
and flush/invalidate the memory regions to address this issue.

This solution is based in a previous work from Clemens Gruber in
commit 598e9dccc7 ("crypto/fsl: fix BLOB encapsulation and
decapsulation")

Reported-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-23 11:21:20 -08:00
Rajesh Bhagat
554d33f3db ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-23 11:20:03 -08:00
Tom Rini
a516416d75 Patch queue for efi - 2018-01-23
This time around we have a lot of EFI patches from Heinrich.
 Highlights are:
 
   - Allow EFI applications to register as drivers
   - Allow exposure of U-Boot block devices from an EFI payload
   - Compatibility improvements
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-01-23

This time around we have a lot of EFI patches from Heinrich.
Highlights are:

  - Allow EFI applications to register as drivers
  - Allow exposure of U-Boot block devices from an EFI payload
  - Compatibility improvements
2018-01-23 07:59:43 -05:00
Heinrich Schuchardt
05ef48a248 efi_driver: EFI block driver
This patch provides
* a uclass for EFI drivers
* a EFI driver for block devices

For each EFI driver the uclass
* creates a handle
* adds the driver binding protocol

The uclass provides the bind, start, and stop entry points for the driver
binding protocol.

In bind() and stop() it checks if the controller implements the protocol
supported by the EFI driver. In the start() function it calls the bind()
function of the EFI driver. In the stop() function it destroys the child
controllers.

The EFI block driver binds to controllers implementing the block io
protocol.

When the bind function of the EFI block driver is called it creates a
new U-Boot block device. It installs child handles for all partitions and
installs the simple file protocol on these.

The read and write functions of the EFI block driver delegate calls to the
controller that it is bound to.

A usage example is as following:

U-Boot loads the iPXE snp.efi executable. iPXE connects an iSCSI drive and
exposes a handle with the block IO protocol. It calls ConnectController.

Now the EFI block driver installs the partitions with the simple file
protocol.

iPXE uses the simple file protocol to load Grub or the Linux Kernel.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[agraf: add comment on calloc len]
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-22 23:09:14 +01:00
Adam Ford
6574864df8 Convert CONFIG_ROCKCHIP_USB2_PHY to Kconfig
This converts the following to Kconfig:
   CONFIG_ROCKCHIP_USB2_PHY

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:30 -05:00
Adam Ford
b9b500b0f9 Convert CONFIG_OMAP_USB_PHY to Kconfig
This converts the following to Kconfig:
   CONFIG_OMAP_USB_PHY

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:30 -05:00
Adam Ford
3b9e2a2520 Convert CONFIG_TWL4030_USB to Kconfig
This converts the following to Kconfig:
   CONFIG_TWL4030_USB

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:30 -05:00
Adam Ford
26410c1517 Convert CONFIG_DAVINCI_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_DAVINCI_SPI

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:30 -05:00
Adam Ford
e13a9dc370 Convert CONFIG_USB_MUSB_HCD et al to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_MUSB_HCD
   CONFIG_USB_MUSB_UDC
   CONFIG_USB_DAVINCI
   CONFIG_USB_OMAP3
   CONFIG_USB_DA8XX
   CONFIG_USB_AM35X

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:29 -05:00
Adam Ford
86362221fc Convert CONFIG_USB_MUSB_OMAP2PLUS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_MUSB_OMAP2PLUS
   CONFIG_USB_MUSB_AM35X
   CONFIG_USB_MUSB_DSPS
   CONFIG_USB_MUSB_PIO_ONLY

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:29 -05:00
Giulio Benetti
3900b45125 sunxi: Fix display timing flags
flags member of struct timing was not initialized,
this took to unpredictable behaviour of display flags,
such DISPLAY_FLAGS_HSYNC_HIGH instead of _LOW etc.

Init timing->flags = 0

Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-22 13:53:08 +05:30
Benoît Thébaudeau
b9b4f146c9 mmc: fsl_esdhc: Fix i.MX53 eSDHCv3 clock
Commit 4f425280fa ("mmc: fsl_esdhc: Allow all supported prescaler
values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR mode on
i.MX, thus bypassing the SD clock frequency prescaler, in order to be
able to get higher SD clock frequencies in some contexts. However, that
commit missed the fact that this value is illegal on the eSDHCv3
instance of the i.MX53. This seems to be the only exception on i.MX,
this value being legal even for the eSDHCv2 instances of the i.MX53.

Fix this issue by changing the minimum prescaler value for the single
instance of the i.MX53 eSDHCv3 controller.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-22 14:17:13 +09:00
Jaehoon Chung
9546eb92cb mmc: fix the wrong disabling clock
When power is off, clock is not disabling.
Because it's passed to 1, mmc->clock should be set to f_min value.
Some drivers can't initialize the eMMC/SD card with current status.

This patch is to fix the disabling clock value to 0.

Fixes: 2e7410d76a ("mmc: disable the mmc clock during power off")

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2018-01-22 14:15:34 +09:00
Masahiro Yamada
61f2e5ee12 mmc: sdhci: change data transfer failure into debug message
During the tuning, drivers repeat data transfer, changing timing
parameters in the controller hardware.  So, the tuning commands
(CMD19 for SD, CMD21 for eMMC) fail, and this is not a problem
at all.

Showing "Error detected..." in normal operation just make users
upset.  This should not be shown.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
dd43e2a6bd mmc: sdhci-cadence: add HS200 support
Add HS200 timing setting and the MMC tuning callback.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
4041bf7f8a mmc: sdhci-cadence: call mmc_of_parse()
This is needed to parse more capabilities such as mmc-hs200-1_8v.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
954a963146 mmc: sdhci-cadence: use bitfield access macros for cleanup
This driver is a counterpart from the one in Linux.  Follow the
clean-up I did in Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
be165fbbf1 mmc: sdhci: do not overwrite host_caps in sdhci_setup_cfg()
This line overwrites host_cap that has been set by drivers and/or
helpers like mmc_of_parse().  Accumulate capabilities flags.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
4b28f7bc93 mmc: let mmc_of_parse() fail for insane bus-width value
You must fix your DT if it specifies insane bus-width, for example,
  bus-width = <3>;

debug() is not displayed in usual configuration, so people will not
even notice weirdness.  Use dev_err() instead, then let it fail.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
c42ee367fd mmc: do not overwrite cfg->f_max if "max-frequency" if missing
mmc_of_parse() in U-Boot is a pussy helper; it sets cfg->f_max to
52MHz even if DT does not provide "max-frequency" at all.  This can
overwrite cfg->f_max that may have been set to a reasonable default.

As the DT binding says, "max-frequency" is an optional property.
Do nothing if DT does not specify it.  This is the behavior of
mmc_of_parse() in Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Masahiro Yamada
3ab48f6223 dm: add dev_read_u32()
dev_read_u32_default() always returns something even when the property
is missing.  So, it is impossible to do nothing in the case.  One
solution is to use ofnode_read_u32() instead, but adding dev_read_u32()
will be helpful.

BTW, Linux has an equvalent function, device_property_read_u32();
it is clearer that it reads a property.  I cannot understand the
behavior of dev_read_u32() from its name.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-22 14:11:58 +09:00
Mario Six
29d11b8838 core: Make device_is_compatible live-tree compatible
Judging from its name and parameters, device_is_compatible looks like it
is compatible with a live device tree, but it actually isn't.

Make it compatible with a live device tree.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
147c607448 core: Add {ofnode, dev}_translate_address functions
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
83a462a5e3 core: read: Fix style violations
There are some whitespace-related style violations in read.c; fix those.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
51db287a14 core: ofnode: Fix style violations
There are some style violations in ofnode.c; fix those.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
fcca9db819 clk: Makefile: Sort entries alphabetically
The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
7fe1b063d8 clk: Remove superfluous gd declarations
The clk uclass was converted to support a live device tree recently,
hence the global data pointer declarations are no longer needed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
e2db9e7a06 clk: clk_fixed_rate: Fix style violation
Fix a mis-indented function call in clk_fixed_rate.c

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
268453be7c clk: clk-uclass: Fix style violations
checkpatch.pl complains that the clk_ops structures used in clk-uclass.c
ought to be const, so we mark them as const.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-21 10:01:02 -07:00
Mario Six
286ede6515 drivers: core: Add translation in live tree case
The function dev_read_addr calls ofnode_get_addr_index in the live tree
case, which does not apply bus translations to the address read from the
device tree. This results in illegal addresses on boards that rely on
bus translations being applied.

Fix this situation by applying bus translations in the live tree case as
well.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Stephen Warren <swarren@nvidia.com>
2018-01-21 10:01:02 -07:00
Tom Rini
557767ed29 Merge git://git.denx.de/u-boot-marvell 2018-01-20 08:39:47 -05:00
Tom Rini
c4cb6e64bf Merge git://git.denx.de/u-boot-arc 2018-01-19 16:07:36 -05:00
Patrice Chotard
ae74de0dfd serial: stm32: Rename serial_stm32x7.c to serial_stm32.c
Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-01-19 15:49:32 -05:00
Tom Rini
bb2277b3ee GPIO: tca642x: Rework to not include commands in SPL
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.

Cc: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:29 -05:00
Tom Rini
0d097b774d GPIO: pca953x: Rework to not include commands in SPL
The command portion of the GPIO driver can only be used in full SPL so
re-work to guard the command related portions and mark it as static.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-19 15:49:29 -05:00
Tero Kristo
72b7af5a04 drivers: dma: ti-edma3: add support for memory fill
Add support for simple memory fill operation. With large data sizes
it is much faster to use EDMA for memory fill rather than CPU.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-01-19 15:49:25 -05:00
Kishon Vijay Abraham I
29171dcfaa mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit
omap_hsmmc driver uses "|" in a couple of places for disabling a bit.
While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a
_mask_ argument to take care of resetting a bit), it's incorrectly used
for resetting flags in "omap_hsmmc_send_cmd".

Fix it here by using "&= ~()" to reset a bit.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:23 -05:00
Kishon Vijay Abraham I
866bb98468 mmc: omap_hsmmc: Enable Auto command (CMD12) enable
Instead of sending STOP TRANSMISSION command from MMC core, enable
the auto command feature so that the Host Controller issues CMD12
automatically when last block transfer is completed.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:23 -05:00
Kishon Vijay Abraham I
f0d53e88a6 mmc: omap_hsmmc: Add support for DMA (ADMA2)
The omap hsmmc host controller can have the ADMA2 feature. It brings better
read and write throughput.
On most SOC, the capability is read from the hl_hwinfo register. On OMAP3,
DMA support is compiled out.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-19 15:49:17 -05:00
Chris Packham
672e559830 ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
8bddf678db ddr: marvell: update additional ODT setting
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
2efd27f76a ddr: marvell: use correct TREFI value
The ternary operation had the HIGH/LOW values the
wrong way round. Update it to use the correct value.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Chris Packham
dbaf09590d ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
Eugeniy Paltsev
320c8a1a86 ARC: HSDK: CGU: Add 'Hz' when printing clock frequency
Add 'Hz' when printing clock frequency in error messages.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
f6d7812d8d ARC: HSDK: CGU: Use plat data instead of priv data
Correctly allocate hsdk_cgu_clk private data structure using
priv_auto_alloc_size instead of platdata_auto_alloc_size.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Eugeniy Paltsev
075cbae163 ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options:
instead of changing only IDIV divider settings adjust also domain PLL
settings.

Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19 17:59:35 +03:00
Jean-Jacques Hiblot
741726ae4c Revert "omap_hsmmc: update struct hsmmc to accommodate omap3 from DT"
This reverts commit 46831c1a4c.
This reserved area at the beginning of struct hsmm, will be used later to
support ADMA

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-18 22:04:21 -05:00
Tom Rini
086ebcd40e Merge git://git.denx.de/u-boot-fsl-qoriq 2018-01-17 13:48:35 -05:00
Peng Fan
fb0128736b i2c: mxc_i2c: Use or operation
The operation should be OR, not BIT OR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-01-16 06:59:39 +01:00
Peng Fan
0074d4bf2d i2c: lpi2c: do not add 4 for bus seq
The number 4 is dedicated on i.MX7ULP, but lpi2c will be reused on i.MX8,
4 is not valid. The seq number could be configured by alias node.

The following patch will use i2c4 as the begin for i.MX7ULP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-16 06:58:59 +01:00
Tom Rini
fdb6c3232f Merge git://git.denx.de/u-boot-net 2018-01-15 19:01:23 -05:00
Tom Rini
8e9801c283 Merge git://git.denx.de/u-boot-imx 2018-01-15 16:44:18 -05:00
Jorge Ramirez-Ortiz
0689eb7470 db410c: replace reset driver with psci
this should be the norm for armv8 platforms.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15 16:29:03 -05:00
Jorge Ramirez-Ortiz
e0cc0b6c6d db820c: enable pmic gpios for pm8994
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15 16:29:02 -05:00
Sriram Dash
a2bbfc5480 serial: lpuart: Proper device identification
Identify and distinguish between platform device type of MX7ULP
and LS1021A.

This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP
support").

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15 12:44:09 -08:00
Zhao Qiang
1e2d2597a6 phy: atheros: set auto-negotiation for AR8021
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:27 -06:00
Nobuhiro Iwamatsu
dcd18eaf61 net: sh-eth: Add to Kconfig and convert
This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:26 -06:00
Nobuhiro Iwamatsu
aae5d237b9 net: sh-eth: Fix misaligned cache operation warning
When we using network on board using sh-eth, it prints a lot of
"CACHE: Misaligned operation at range" messages.
This commit fixes this problem.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:26 -06:00
Nobuhiro Iwamatsu
fbfb511548 net: sh-eth: Change read/write() param to struct sh_eth_info
This changes Change structure used in sh_eth_read and sh_eth_write function
from struct sh_eth_dev to struct sh_eth_info. This is necessary to convert
to Driver Model.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:25 -06:00
Nobuhiro Iwamatsu
9b5f9ecf6e net: sh-eth: Remove bd_t from sh_eth_config()
bd_t is not used in sh_eth_config(). This deletes bd_t from sh_eth_config()

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:24 -06:00
Nobuhiro Iwamatsu
dc14867d0f net: sh-eth: Fix coding style checked by checkpatch.pl
This fixes the chord style checked by checkpatch.pl.
Details of change details are as follows:

 - Fix typo
    Change from alligned to aligned.
 - Remove whitespace before ','
 - Add spaces preferred around that '|'
 - Fix missing a blank line after declarations
 - Remove space after a cast declaration
 - Fix format of block comments
 - Add a blank line after function/struct/union/enum declarations

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:24 -06:00
Florian Fainelli
f3d78fbfaf net: phy: b53: Add b53_reg read/write commands
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:22 -06:00
Florian Fainelli
7a9ca9db40 net: designware: Pad small packets
Make sure that we pad small packets to a minimum length of 60 bytes
(without FCS). This is necessary to interface with Ethernet switches
that will reject RUNT frames unless padded correctly.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:21 -06:00
Florian Fainelli
137963d71a net: phy: Add Broadcom BCM53xx switch driver
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.

This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-01-15 12:05:21 -06:00
Patrice Chotard
ba1f966725 net: designware: add clock support
This implementation manages several clocks, disable and
free all of them in case of error during probe and in remove
callback.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:20 -06:00
Patrice Chotard
ea8cd652a7 dm: core: add missing dev_count_phandle_with_args()
Add missing dev_count_phandle_with_args() to avoid
compilation issue.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:19 -06:00
Jason Brown
32ac8b0bba net: mvneta - Fixed recv() when multiple packets have arrived.
This patch fixes a problem in the mvneta driver where if more than
one packet arrives between calls to mvneta_recv(), the additional
descriptors will be marked as free even though only one descriptor
has been read and processed from the receive queue.  This causes
the additional packet(s) to be delayed until the next packet arrives.
>From this point on all packets will be delayed because the receive
queue will contain unprocessed packets but the hardware shows no
busy descriptors.

Signed-off-by: Jason Brown <jason.brown@apcon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:19 -06:00
Chris Brandt
33bab10457 net: miiphybb: fix casting error
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.

Fixes: dfcc496ed7 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:17 -06:00
Chris Brandt
f6ac626c8a net: sh-eth: remove sh_eth_offset_rz table
First, this table could never be included in the build anyway because
SH_ETH_TYPE_RZ is not defined until later in the file.
Second, the register PIR was missing, so PHY MDIO never worked.
Third, after adding the PIR register, the table is EXACTLY the same as
sh_eth_offset_gigabit, so there is no value to it.

Therefore, just delete it use the gigabit one.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:17 -06:00
Chris Brandt
5ad565b0d1 net: sh-eth: fix inl and outl definitions
The macros inl and outl maybe already be defined from file
arch/arm/include/asm/io.h so there may be no reason to define them.
And if you do try defined them here, you get a redefined complier warning.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:16 -06:00
Lukasz Majewski
ce27eb9b40 net: phy: marvell: Add functions to read PHY's extended registers
This commit allows extended Marvell registers to be read with:

foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011

The above code changes the way ETH connector LEDs blink.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:16 -06:00
Joe Hershberger
3cacc6a772 net: Fix buffer overrun error in netconsole
Need to not access the byte after the input_buffer.

Reported-by: Coverity (CID: 144423)
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:14 -06:00
Wilson Lee
4bf56913d0 net: macb: Add support for Xilinx Zynq SoC
Although Xilinx Zynq SoC was using MACB similar hardware. However,
U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
to add support for the Xilinx Zynq SoC to the existing MACB network
driver.

This patch is to add Zynq GEM DMA Config, provide callback
function for different linkspeed for case of using Xilinx Zynq
Programmable Logic as GMII to RGMII converter.

This patch convert the return value to use error codes.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-01-15 12:05:14 -06:00
Rob Clark
f2006808f0 dm: core: parse chosen node
This is the node that would contain, for example, the framebuffer setup
by an earlier stage.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-01-15 11:35:38 -05:00
Jorge Ramirez-Ortiz
210d959294 spmi: msm: display the PMIC Arb version (debug)
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2018-01-15 11:35:37 -05:00
Tom Rini
3dde8f2037 Merge git://git.denx.de/u-boot-mmc 2018-01-14 22:26:38 -05:00
Peng Fan
db359efd59 mmc: fsl_esdhc: Fix eMMC 1.8v setting issue
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.

Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-13 00:08:44 +09:00
Tom Rini
8c0bb85824 power: Rearrange code to guard power command with CONFIG_SPL_BUILD guard
In order to discard this code when unused in SPL we need to guard the
command with a check for CONFIG_SPL_BUILD and we rearrange the code
slightly to make this cleaner.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-13 00:07:57 +09:00
Koen Vandeputte
f57263ee9b drivers: pci: imx: fix enumeration logic error
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-01-12 14:28:04 +01:00
Peng Fan
afe8e1b033 spi: fsl_qspi: support i.MX6UL/6ULLL/7D
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.

The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.

Add the compatible entry for 6ul/7d.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12 14:28:04 +01:00
Peng Fan
67b71df277 pci: imx: request gpio before use
Before use GPIO, we need to request gpio first. Free gpio after use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12 14:28:04 +01:00
Peng Fan
8df42bee0e misc: mxc_ocotp: check fuse word before programming on i.MX7ULP
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to
write once, because they use ECC mode. Multiple writes may damage
the ECC value and cause a wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only
can write when the word value is 0.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12 14:28:04 +01:00
Jean-Jacques Hiblot
b7a6e2c9c3 mmc: remove hc_wp_grp_size from struct mmc if not needed
hc_wp_grp_size is needed only if hardware partitionning is used.
On ARM removing it saves about 30 bytes of code space.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
173c06dfcc mmc: don't read the size of eMMC enhanced user data area in SPL
This information is only used by the "mmc info" command.
On ARM removing this information from SPL saves about 140 of code space.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
e6fa5a5461 mmc: compile out erase and write mmc commands if write operations are not enabled
Also remove erase_grp_size and write_bl_len from struct mmc as they are
not used anymore. On ARM, removing them saves about 100 bytes of code
space in SPL.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
5b2e72f327 mmc: read ssr only if MMC write support is enabled
The content of ssr is useful only for erase operations.
on ARM, removing sd_read_ssr() saves around 300 bytes.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
d6400c3f85 mmc: add a Kconfig option to enable the support for MMC write operations
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
58a6fb7b04 mmc: reworked version lookup in mmc_startup_v4
Using a table versus a switch() structure saves a bit of space

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:24 +09:00
Jean-Jacques Hiblot
baef2070a4 mmc: compile out more code if support for UHS and HS200 is not enabled
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:23 +09:00
Jean-Jacques Hiblot
9b79dbd201 mmc: atmel: when sending a data command, use the provided block size
struct mmc_data contains the block size to use for the data transfer.
Use this information instead of using the default value or the block length
information stored in struct mmc.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:23 +09:00
Jean-Jacques Hiblot
49f89252ed dm: mmc: sandbox: Update SD card emulation
The SDcard initialization procedure does a few more things than it did earlier:
* switch the bus width even for 1-bit bus width
* check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC)

Update the SD simulator to handle those requests gracefully.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
cf17789e07 mmc: make optional the support for eMMC hardware partitioning
Not all boards have an eMMC and not all users have a need for this.
Allow to compile it out. By default it is still included.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
f99c2efe56 mmc: make UHS and HS200 optional
Supporting USH and HS200 increases the code size as it brings in IO voltage
control, tuning and fatter data structures.
Use Kconfig configuration to select which of those features should be
built in.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
d8e3d42089 mmc: convert most of printf() to pr_err() and pr_warn()
This allows to compile out the log message by tweaking the LOGLEVEL.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
f7d5dffc65 mmc: don't use malloc_cache_aligned()
Not using this function reduces the size of the binary. It's replaces by
a standard malloc() and the alignment requirement is handled by an
intermediate buffer on the stack.

Also make sure that the allocated buffer is freed in case of error.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
1de06b9fa5 mmc: fix for old MMCs (below version 4)
The ext_csd is allocated only for MMC above version 4. The compare will
crash or fail for older MMCs.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
1da8eb598f mmc: all hosts support 1-bit bus width and legacy timings
Make sure that those basic capabilities are advertised by the host.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
00e446fa04 mmc: Fixed a problem with old sd or mmc that do not support High speed
As the legacy modes were not added to the list of supported modes, old
cards that do not support other modes could not be used.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
7abff2c3b3 dm: mmc: update mmc_of_parse()
* convert to livetree API
* don't fail because of an invalid bus-width, instead default to 1-bit.
* recognize 1.2v DDR and 1.2v HS200 flags

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
52d241dfba mmc: dump card and host capabilities if debug is enabled
This is a useful information while debugging the initialization process or
performance issues.
Also dump this information with the other mmc info if the verbose option
is selected

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jaehoon Chung
ef1614acf8 mmc: meson_gx_mmc: fix the complie error
mmc_set_clock() is changed.
This patch is for fixing complie error.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-12 18:11:04 +09:00
Kishon Vijay Abraham I
9215ef5ed5 dm: mmc: Add a library function to parse generic dt binding
Add a new function to parse host controller dt node and
set mmc_config. This function can be used by mmc controller
drivers to set the generic mmc_config.
This function can be extended to set other UHS mode caps
once UHS mode support is added.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
9815e3ba80 mmc: add a library function to send tuning command
HS200/SDR104 requires tuning command to be sent to the card.
Add a simple function to send tuning command and to read and
compare the received data with the tuning block pattern.
This function can be used by platform driver to perform DLL
tuning.
This patch is similar to
commit 996903de92f0 ("mmc: core: add core-level function for
sending tuning commands") added in linux kernel.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Jean-Jacques Hiblot
bc1e3272ff mmc: use the right voltage level for MMC DDR and HS200 modes
HS200 only supports 1.2v and 1.8v signal voltages. DDR52 supports 3.3v/1.8v
or 1.2v signal voltages.
Select the lowest voltage available when using those modes.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Kishon Vijay Abraham I
83dc42271f mmc: Retry some MMC cmds on failure
With certain SD cards like Kingston 8GB/16GB UHS card, it is seen that
MMC_CMD_ALL_SEND_CID cmd fails on first attempt, but succeeds
subsequently. Therefore, retry MMC_CMD_ALL_SEND_CID cmd a few time
as done in Linux kernel.
Similarly, it is seen that MMC_CMD_SET_BLOCKLEN may fail on first
attempt, therefore retry this cmd a few times as done in kernel.

To make it clear that those are optionnal workarounds, a new Kconfig
option 'MMC_QUIRKS' is added (enabled by default).

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00