Commit graph

129 commits

Author SHA1 Message Date
Benoît Thébaudeau
b9b4f146c9 mmc: fsl_esdhc: Fix i.MX53 eSDHCv3 clock
Commit 4f425280fa ("mmc: fsl_esdhc: Allow all supported prescaler
values") made it possible to set SYSCTL.SDCLKFS to 0 in SDR mode on
i.MX, thus bypassing the SD clock frequency prescaler, in order to be
able to get higher SD clock frequencies in some contexts. However, that
commit missed the fact that this value is illegal on the eSDHCv3
instance of the i.MX53. This seems to be the only exception on i.MX,
this value being legal even for the eSDHCv2 instances of the i.MX53.

Fix this issue by changing the minimum prescaler value for the single
instance of the i.MX53 eSDHCv3 controller.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-22 14:17:13 +09:00
Peng Fan
db359efd59 mmc: fsl_esdhc: Fix eMMC 1.8v setting issue
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.

Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-13 00:08:44 +09:00
Kishon Vijay Abraham I
35f6782055 mmc: add a new mmc parameter to disable mmc clock
mmc clock has to be disabled in certain cases like during
the voltage switch sequence. Modify mmc_set_clock function
to take disable as an argument that signifies if the
clock has to be enabled or disabled.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12 18:11:04 +09:00
Benoît Thébaudeau
bcfb365375 mmc: fsl_esdhc: Fix PIO timeout
The following error has been observed on i.MX25 with a high-speed SDSC
card:
    Data Write Failed in PIO Mode.

It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.

This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-11-07 10:26:27 +01:00
Simon Glass
e7881d85a9 dm: mmc: Drop CONFIG_DM_MMC_OPS
All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:59:55 +09:00
Simon Glass
5248930ebf dm: imx: cm_fx6: Enable more driver model support
Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
653282b567 dm: mmc: fsl_esdhc: Update to support MMC operations
This driver does not currently support CONFIG_DM_MMC_OPS. Update it to
fully convert it to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
4aac33f510 dm: mmc: fsl_esdhc: Update to support livetree
Update this driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
d6eb25e987 dm: mmc: fsl_esdhc: Drop mmc_init() call from fsl_esdhc_init()
We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
e88e1d9c04 dm: mmc: fsl_esdhc: Set up platform data
With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
201e828b22 dm: mmc: fsl_esdhc: Detect init failure
Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
446e077a21 dm: mmc: fsl_esdhc: Detect reset failure
Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
9586aa6ea3 dm: mmc: fsl_esdhc: Set up common versions of operations
Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Simon Glass
09b465fd0f dm: mmc: fsl_esdhc: Pass private data to internal functions
With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-17 16:44:17 +09:00
Yang Li
590e87d1a6 mmc: fsl_esdhc: not always setting esdhc fdt status to okay
We shouldn't always change the status to okay.  There could be
situations that the esdhc is intentionally disabled in the device
tree.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
York Sun
9bb272e90a driver: mmc: fsl_esdhc: Fix compiling warning
Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-08-09 09:11:29 -07:00
Peng Fan
f34ccce50a mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Peng Fan
4483b7eb88 dm: mmc: fsl_esdhc: handle vqmmc supply
Handle vqmmc supply. Some boards have a fixed I/O voltage
at 1.8V for emmc, so the usdhc also needs to be configured
as 1.8V by setting VSELECT bit. The vs18_enable is the one
that used to checking whether setting VSELECT or not in
the driver. So if vqmmc supply is 1.8V, set vs18_enable,
the driver will set VSELECT.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-07-12 09:44:22 +02:00
Peng Fan
32a9179f3a mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.

We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-07-12 09:44:22 +02:00
Tom Rini
821560fd8e Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/imx6qdl_icore_rqs.h
	include/configs/imx6ul_geam.h
	include/configs/imx6ul_isiot.h
2017-06-27 09:32:37 -04:00
Simon Glass
150c5afe5b dm: gpio: Add live tree support
Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01 07:03:10 -06:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Jagan Teki
2e87c440f6 mmc: fsl_esdhc: Move non DM_MMC code in #ifndef CONFIG_DM_MMC
Don't build non DM_MMC code when DM_MMC defined so move
them into #ifndef CONFIG_DM_MMC

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2017-05-31 10:21:24 +02:00
Benoît Thébaudeau
4f425280fa mmc: fsl_esdhc: Allow all supported prescaler values
On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
can divide by up to 512. Allow both of these settings.

The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).

Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-05-31 10:14:00 +02:00
Peng Fan
b60f14574e mmc: fsl_esdhc: support i.MX7ULP
Add compatible property for i.MX7ULP.
Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-03-17 09:27:08 +01:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Tom Rini
0675f992db Merge git://git.denx.de/u-boot-fsl-qoriq 2017-01-19 12:22:23 -05:00
Yangbo Lu
fce1e16c55 mmc: fsl_esdhc: move 'status' property fixup into a weak function
Move fdt fixup of 'status' property into a weak function. This allows
board to define 'status' fdt fixup by themselves.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:46:30 -08:00
Yangbo Lu
a6473f8e3f mmc: fsl_esdhc: add 'fsl, esdhc' into of_match table
This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:20 -08:00
Yangbo Lu
fc8048a88e mmc: fsl_esdhc: make GPIO support optional
There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:14 -08:00
Jaehoon Chung
07b0b9c00c mmc: change the set_ios return type from void to int
To maintain consistency, set_ios type of legacy mmc_ops changed to int.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-01-11 19:40:13 +09:00
Peng Fan
35ae99467d dm: mmc: intialize dev when probe
Need to initialize mmc->dev when probe, or will met
"dev_get_uclass_priv: null device", when `mmc dev 1`.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-04 15:41:01 +02:00
Jaehoon Chung
915ffa5213 mmc: use the generic error number
Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
70f862808e mmc: fsl_esdhc: remove the duplicated header file
"mmc.h" is already included. It's duplicated.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:21:25 +09:00
Peng Fan
1483151e84 mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Ye Li
84ecdf6da9 fsl_esdhc: Update clock enable bits for USDHC
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Peng Fan
f53225cce4 mmc: fsl: reset to normal boot mode when eMMC fast boot
When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:53 -07:00
Eddy Petrișor
9702ec00e9 armv8: s32v234: Introduce basic support for s32v234evb
Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>

Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
2016-06-13 08:56:35 -04:00
Yangbo Lu
cc634e2836 mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function
In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:05 -07:00
Peng Fan
96f0407b00 fsl: esdhc: support driver model
Support Driver Model for fsl esdhc driver.

1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
   - Introduce fsl_esdhc_init to be common usage for DM and non-DM
   - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part.
   - The original API for board code is still there, but we use
     'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it.
3. All the functions are changed to use 'struct fsl_esdhc_priv', except
   fsl_esdhc_initialize.
4. Since clk driver is not implemented, use mxc_get_clock to geth
   the clk and fill 'priv->sdhc_clk'.

Has been tested on i.MX6UL 14X14 EVK board:
"
=>dm tree
....
 simple_bus  [ + ]    |   `-- aips-bus@02100000
  mmc        [ + ]    |       |-- usdhc@02190000
  mmc        [ + ]    |       |-- usdhc@02194000
....
=> mmc list
FSL_SDHC: 0 (SD)
FSL_SDHC: 1 (SD)
"

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Hector Palacios <hector.palacios@digi.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-By: Eric Nelson <eric@nelint.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-04-06 08:33:37 -07:00
Yangbo Lu
25503443ee mmc: fsl_esdhc: set Abort command type for CMD12
According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need
to be set an Abort command type when they are sent. So, we remove all
chip-specific #ifdefs and make it available for all platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:13 -08:00
Yangbo Lu
e978a31b63 mmc: fsl_esdhc: increase data transaction timeout to 500ms
The MMC spec says "It is strongly recommended for hosts to implement
more than 500ms timeout value even if the card indicates the 250ms
maximum busy length."  Even the previous value of 300ms is known to
be insufficient for some cards. So, increase the timeout to 500ms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:12 -08:00
Eric Nelson
f0b5f23f32 ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register
The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.

Guard against their usage by hiding the bit mask macros on those
processors.

These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

>From the i.MX6DQ RM:
	To prevent possible glitch on the card clock, clear the
	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
	or DVS in System Control Register) or setting RSTA bit.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Hector Palacios <hector.palacios@digi.com>
2016-01-03 15:21:21 +01:00
Yangbo Lu
bf50be835e mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card
When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:50:29 -08:00
Yangbo Lu
cdc69550d2 mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card
If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:49:51 -08:00
Shaohui Xie
512bdbd46a Powerpc: eSDHC: expand a fix to T4160
commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of
T4240QDS board", T4160 also needs this fix.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:49:32 -08:00
Yangbo Lu
8ef0d5c438 armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Tom Rini
e3d50d4292 fsl_esdhc.c: Always make check_and_invalidate_dcache_range available
This function is called from esdhc_send_cmd so we need it available to
everyone.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-02 10:27:52 -04:00
Peng Fan
4683b22065 mmc:fsl_esdhc invalidate dcache before read
DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.

We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.

With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-07-26 12:17:20 +02:00
Tom Rini
d81572c272 Merge git://git.denx.de/u-boot-mpc85xx 2015-05-05 14:57:23 -04:00