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mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT

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CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2017-06-12 17:50:55 +08:00 committed by Stefano Babic
parent 4483b7eb88
commit f34ccce50a
5 changed files with 1 additions and 9 deletions
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2
board/warp/warp.c
View file

@ -62,7 +62,7 @@ static void setup_iomux_uart(void)
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC2_BASE_ADDR},
{USDHC2_BASE_ADDR, 0, 0, 0, 1},
};
int board_mmc_getcd(struct mmc *mmc)

2
doc/README.fsl-esdhc
View file

@ -20,5 +20,3 @@ Freescale esdhc-specific options
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
by ESDHC IP's endian mode or processor's endian mode.
- CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.

4
drivers/mmc/fsl_esdhc.c
View file

@ -673,10 +673,6 @@ static int esdhc_init(struct mmc *mmc)
/* Set timout to the maximum value */
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
#endif
if (priv->vs18_enable)
esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);

1
include/configs/warp.h
View file

@ -23,7 +23,6 @@
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_SUPPORT_EMMC_BOOT

1
scripts/config_whitelist.txt
View file

@ -3208,7 +3208,6 @@ CONFIG_SYS_FSL_ERRATUM_A_004934
CONFIG_SYS_FSL_ESDHC_ADDR
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_ESDHC_NUM