The P2020DS build had grown too large, and video support isn't enabled
in almost any other Freescale board. Disabling it allows us to keep
building, and provides options for reenabling it later.
Signed-off-by: Andy Fleming <afleming@freescale.com>
BSC9132QDS is a Freescale reference design board for BSC9132 SoC.
BSC9132 SOC is an integrated device that targets the evolving Microcell,
Picocell, and Enterprise-Femto base station market subsegments.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
BSC9132QDS Overview
--------------------
2Gbyte DDR3 (on board DDR), Dual Ranki
32Mbyte 16bit NOR flash
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
SD slot
USB-ULPI
eTSEC1: Connected to SGMII PHY
eTSEC2: Connected to SGMII PHY
PCIe
CPRI
SerDes
I2C RTC
DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In order to be able to build a u-boot.pbl image, both the
CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be
defined.
This patch sets these two files for the P2041RDB board.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.
B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
USB controller in uboot is a required feature for MPC8544DS. Without this
support there is no 'usb' command in uboot.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The controller interleaving only takes the usable memory mapped to cs0. In
the case of bank interleaving not enabled, only half of dual-rank DIMM will
be used.
For single-rank DIMM bank interleaving will be auto disabled.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.
So Fix the Address Mask Register initilisation as 4K
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
"CONFIG_SYS_I2C_BUS" and "CONFIG_SYS_I2C_BUS_SELECT" don't appear anywhere
outside of config files.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
In commit abbab70 we added a prototype for hw_watchdog_init, in a
Freescale i.MX watchdog driver. We did not however guard it with an
__ASSEMBLY__ check and broke some platforms. Move this to the end of
the file with other prototypes and guard it.
Signed-off-by: Tom Rini <trini@ti.com>
Since commit de7d02aeb (mx6qsabresd: add usdhc2 and usdhc4 support)
SDHC3 device node is no longer 0, which breaks loading a uImage from SDHC3.
Fix it by adapting the default environment to use CONFIG_SYS_MMC_ENV_DEV as the
correct mmc node for loading the kernel from.
While at it, go back to using SDHC3 as the default mmc, since we have Yocto
images that generate an SD card containing U-boot,kernel and rootfs, so it is
more convenient to keep using SDHC3 as it was originally.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
For a generic environment, we shouldn't have a fixed rootfs filesystem
so we drop it from env.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Add dataflash boot support on at91sam9x5ek board
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
We enable console multiplexing and use both serial and LCD for stdout/stderr.
Initially, u-boot output console is observed via serial port.
If you also have a DP panel connected onto your SMDK5250 board,
you can switch to LCD console by typing "setenv stdout lcd".
You can always switch back to serial using "setenv stdout serial".
You can switch error console(stderr) as well, using similar commands.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
u-boot compilation fails for smdk5250 when we deselect CONFIG_LCD
from the main config file.
Following error was observed:
drivers/video/libvideo.o: In function `exynos_lcd_init':
/home/ajay/u-boot-samsung/drivers/video/exynos_fb.c:68: undefined reference to `lcd_set_flush_dcache'
This is because exynos video drivers have dependency on CONFIG_LCD.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
IGEP board PC16550D (ns16550) UART doesn't set the
Transmitter Empty (TEMT) Bit in SPL. This makes
U-Boot to hang while waiting for TEMT. Add the
CONFIG_SYS_NS16550_BROKEN_TEMT config option to
avoid this issue.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
When booting an IGEPv2 board from NAND with SPL, U-Boot hangs
trying to read the OMAP General Purpose Memory Controller (GPMC).
The reason is that the GPMC initialization function is called
inside spl_board_init() and this function is only executed when
CONFIG_SPL_BOARD_INIT is defined.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Some boards want to report more than just memory size. For example, it
might be useful to display the memory type (DDR2, DDR3) or manufacturer.
Add a weak function to support this requirement, accessed through a new
'meminfo' command.
Any example of the DRAM: output is below, just for illustration:
SMDK5250 # meminfo
DRAM: 2 GiB Elpida DDR3 @ 800MHz
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for SST 4KB sector granularity.
Many recent SST flashes, i.e. SST39VF3201B and similar of this family
are declared CFI-conformant from SST. They support CFI query, but implement
2 different sector sizes in the same memory: a 64KB sector (they call it
"block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector",
erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh
of cfi query struct, detects a number of secotrs for the 4KB granularity
(flinfo shows it).
For all other aspects, they are CFI compliant, so, as Linux do, i think
it's a good idea to handle these chips in the CFI driver, with a fixup
to allow 4KB granularity, as should be expected, instead of 64KB.
Signed-off-by: Angelo Dureghello <sysamfw@gmail.com>
Signed-off-by: Stefan Rose <sr@denx.de>
Add panel_info structure required by LCD driver
and DP panel platdata for SMDK5250.
Add GPIO configuration for LCD.
Enable FIMD and DP support on SMDK5250.
DP Panel size: 2560x1600.
We use 16BPP resolution to get LCD console.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chomium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add required compatible information for PMIC
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This will fix the following error:
---8<---
UBIFS error (pid 0): ubifs_mount: Error reading superblock on volume 'ubi:root' errno=-12!
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: prafulla@marvell.com
Cc: dimax.main@gmail.com
Tested-by: Alex Xol <dimax.main@gmail.com>
Instead of using the serverip we get from the DHCP server, implicitly use
the broadcast address, which is automatically set when no ncip environment
variable is set. That way it isn't necessary to use a special DHCP
configuration to set the netconsole peer.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
These variables are only used if CONFIG_SYS_CONSOLE_IS_IN_ENV
is set. This isn't the case, so we can drop them safely.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Move all the C runtime setup code from every start.S
in arch/arm into arch/arm/lib/crt0.S. This covers
the code sequence from setting up the initial stack
to calling into board_init_r().
Also, rewrite the C runtime setup and make functions
board_init_*() and relocate_code() behave according to
normal C semantics (no jumping across the C stack any
more, etc).
Some SPL targets had to be touched because they use
start.S explicitly or for some reason; the relevant
maintainers and custodians are cc:ed.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Add required compatible information for USB
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add required compatible information for SPI driver.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds FDT support to the sound driver.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add required compatible information for sound driver.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
