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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-01-08 14:59:37 +01:00
commit 7528cf5f01
14 changed files with 172 additions and 42 deletions
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2
board/freescale/mx35pdk/mx35pdk.c
View file

@ -274,7 +274,7 @@ int board_late_init(void)
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
gpio_direction_output(37, 1);
gpio_direction_output(IMX_GPIO_NR(2, 5), 1);
}
val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;

84
board/freescale/mx53loco/mx53loco.c
View file

@ -343,14 +343,13 @@ static void setup_iomux_i2c(void)
static int power_init(void)
{
unsigned int val;
int ret = -1;
int ret;
struct pmic *p;
int retval;
if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
retval = pmic_dialog_init(I2C_PMIC);
if (retval)
return retval;
ret = pmic_dialog_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("DIALOG_PMIC");
if (!p)
@ -359,20 +358,39 @@ static int power_init(void)
/* Set VDDA to 1.25V */
val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
if (ret) {
printf("Writing to BUCKCORE_REG failed: %d\n", ret);
return ret;
}
ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
val |= DA9052_SUPPLY_VBCOREGO;
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
if (ret) {
printf("Writing to SUPPLY_REG failed: %d\n", ret);
return ret;
}
/* Set Vcc peripheral to 1.30V */
ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
if (ret) {
printf("Writing to BUCKPRO_REG failed: %d\n", ret);
return ret;
}
ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
if (ret) {
printf("Writing to SUPPLY_REG failed: %d\n", ret);
return ret;
}
return ret;
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
retval = pmic_init(I2C_PMIC);
if (retval)
return retval;
ret = pmic_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("FSL_PMIC");
if (!p)
@ -382,28 +400,50 @@ static int power_init(void)
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
ret = pmic_reg_write(p, REG_SW_0, val);
if (ret) {
printf("Writing to REG_SW_0 failed: %d\n", ret);
return ret;
}
/* Set VCC as 1.30V on SW2 */
pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
ret |= pmic_reg_write(p, REG_SW_1, val);
ret = pmic_reg_write(p, REG_SW_1, val);
if (ret) {
printf("Writing to REG_SW_1 failed: %d\n", ret);
return ret;
}
/* Set global reset timer to 4s */
pmic_reg_read(p, REG_POWER_CTL2, &val);
val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
ret = pmic_reg_write(p, REG_POWER_CTL2, val);
if (ret) {
printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
return ret;
}
/* Set VUSBSEL and VUSBEN for USB PHY supply*/
pmic_reg_read(p, REG_MODE_0, &val);
val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
ret |= pmic_reg_write(p, REG_MODE_0, val);
ret = pmic_reg_write(p, REG_MODE_0, val);
if (ret) {
printf("Writing to REG_MODE_0 failed: %d\n", ret);
return ret;
}
/* Set SWBST to 5V in auto mode */
val = SWBST_AUTO;
ret |= pmic_reg_write(p, SWBST_CTRL, val);
ret = pmic_reg_write(p, SWBST_CTRL, val);
if (ret) {
printf("Writing to SWBST_CTRL failed: %d\n", ret);
return ret;
}
return ret;
}
return ret;
return -1;
}
static void clock_1GHz(void)
@ -462,12 +502,18 @@ int board_init(void)
mxc_set_sata_internal_clock();
setup_iomux_i2c();
lcd_enable();
return 0;
}
int board_late_init(void)
{
if (!power_init())
clock_1GHz();
print_cpuinfo();
lcd_enable();
return 0;
}

80
board/freescale/mx6qsabresd/mx6qsabresd.c
View file

@ -86,6 +86,20 @@ static void setup_iomux_enet(void)
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -100,28 +114,82 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[1] = {
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
int board_mmc_getcd(struct mmc *mmc)
{
gpio_direction_input(IMX_GPIO_NR(2, 0));
return !gpio_get_value(IMX_GPIO_NR(2, 0));
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
return !gpio_get_value(USDHC2_CD_GPIO);
case USDHC3_BASE_ADDR:
return !gpio_get_value(USDHC3_CD_GPIO);
default:
return 1; /* eMMC/uSDHC4 is always present */
}
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
int i;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return 0;
}
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
printf("Warning: failed to initialize mmc dev %d\n", i);
}
return 0;
}
#endif

2
drivers/mmc/fsl_esdhc.c
View file

@ -577,7 +577,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
return -1;
}
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

2
include/configs/m28evk.h
View file

@ -178,6 +178,8 @@
"512k(environment)," \
"512k(redundant-environment)," \
"4m(kernel)," \
"128k(fdt)," \
"8m(ramdisk)," \
"-(filesystem)"
#else
#define CONFIG_ENV_IS_NOWHERE

1
include/configs/mx35pdk.h
View file

@ -95,6 +95,7 @@
#include <config_cmd_default.h>
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP

4
include/configs/mx51evk.h
View file

@ -34,10 +34,6 @@
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
/*
* Disabled for now due to build problems under Debian and a significant
* increase in the final file size: 144260 vs. 109536 Bytes.
*/
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS

10
include/configs/mx53loco.h
View file

@ -39,6 +39,7 @@
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
@ -112,7 +113,7 @@
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -120,11 +121,8 @@
"uimage=uImage\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot} " \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \

4
include/configs/mx6qsabre_common.h
View file

@ -41,7 +41,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMC
#define CONFIG_CMD_MMC
@ -78,7 +77,7 @@
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -166,7 +165,6 @@
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define CONFIG_OF_LIBFDT

5
include/configs/mx6qsabreauto.h
View file

@ -20,4 +20,9 @@
#include "mx6qsabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#endif /* __MX6QSABREAUTO_CONFIG_H */

2
include/configs/mx6qsabrelite.h
View file

@ -148,7 +148,7 @@
#define CONFIG_PREBOOT ""
#define CONFIG_LOADADDR 0x10800000
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \

6
include/configs/mx6qsabresd.h
View file

@ -25,4 +25,10 @@
#include "mx6qsabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 2 /* eMMC/uSDHC4 */
#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */
#endif
#endif /* __MX6QSABRESD_CONFIG_H */

3
include/image.h
View file

@ -179,6 +179,9 @@
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
/* Reused from common.h */
#define ROUND(a, b) (((a) + (b) - 1) & ~((b) - 1))
/*
* Legacy format image header,
* all data in network byte order (aka natural aka bigendian).

9
tools/imximage.c
View file

@ -515,7 +515,14 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
*header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
/*
* ROM bug alert
* mx53 only loads 512 byte multiples.
* The remaining fraction of a block bytes would
* not be loaded.
*/
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
}
int imximage_check_params(struct mkimage_params *params)