Commit graph

49016 commits

Author SHA1 Message Date
Patrice Chotard
f36bcf2390 arch-stm32: Move gpio.h for STM32 SoCs in include/asm/
Instead to have 3 identical gpio.h for all STM32 SoCs,
migrate them in one file in include/asm.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
bb43fe6e45 arch-stm32f4: Remove fmc.h file
fmc.h file is no more used, remove it.
All FMC related defines are declared in drivers/ram/stm32_sdram.c
which is common to all STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
dd1e3e799a ARM: dts: stm32: limit sdio frequency to 14Mhz for stm32f429i-eval
This avoids the following errors while reading on mmc:
  Read data bytes CRC error: 0x2
  switch to partitions #0, OK
  mmc0 is current device
  Read data bytes CRC error: 0x82002
  ** Unrecognized filesystem type **

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
6243c88448 clk: clk_stm32f: Add DSI clock support
DSI clock is available on STM32F769-disco and
STM32F469-disco board.

Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
5e993508cb clk: clk_stm32f: Add set_rate for LTDC clock
Implement set_rate() for LTDC clock only, set_rate for other
clocks will be added if needed. This is needed by future LTDC driver
improvements.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
e8fb9ed254 clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock
Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
1038e033e1 clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part
Rework the way SDMMC clock get rate is done in a more
generic way :

_ Add stm32_clk_get_pllsai_rate() which give the PLLSAI
  indicated output rate.

_ Add stm32_clk_get_pllsai_vco_rate() which give the VCO
  internal rate.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
651a70e8d5 clk: clk_stm32f: No more need of 48Mhz from PLL_SAI
Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.

A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
526aa92960 clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines
Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
aa230be4bf clk: clk_stm32f: Fix stm32_clk_get_rate()
Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrick Delaunay
167f2c90f6 mmc: stm32: sdmmc2: add support for st, pin-ckinsdmmc_ckin
This patch adds "st,pin-ckin" support to activate sdmmc_ckin feature.
When using an external driver (a voltage switch transceiver),
it's advised to select SDMMC_CKIN feedback clock input to sample
the received data.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrick Delaunay
a72dd8ed95 mmc: stm32: sdmmc2: add hardware flow control support
The hardware flow control functionality is used to avoid
FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDMMC_CK during data transfer and
freeze the SDMMC state machines.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
aa5e3e22f4 board: stm32: switch to DM STM32 timer
Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.

Remove all defines or files previously used for timer usage in
arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx

Enable DM STM32_TIMER for STM32F4/F7 and H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
cd389c03f2 ARM: dts: stm32: Add timer support for STM32F7
Add missing timer node to enable timer5 for STM32F7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
09b335a675 clk: clk_stm32h7: Fix prescaler for Domain 3
d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
b43679482b clk: clk_stm32h7: Fix stm32_clk_get_rate() for timer
For timer clock, an additional prescaler is used which
was not taken into account previously.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
61803a95a1 clk: clk_stm32f: Fix stm32_clk_get_rate() for timer
For timer clock, an additionnal prescaler is used which was
not taken into account previously.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Patrice Chotard
5120a083e7 timer: stm32: Add timer support for STM32 SoCs family
This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Tom Rini
cc66dcdd16 Merge git://git.denx.de/u-boot-rockchip 2018-03-13 19:00:29 -04:00
Tom Rini
ee5f24909f Merge branch 'next' of git://git.denx.de/u-boot-video 2018-03-13 17:32:47 -04:00
Jagan Teki
1e84e44cfe rk3288: vyasa: Add eMMC boot support
RK3288 Vyasa has eMMC boot support, with JP4 open.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:36 +01:00
Jagan Teki
159916f4e8 ARM: dts: rockchip: Add usb otg for rk3288-vyasa
Add usb otg support for rk3288-vyasa, board support usb1 otg
power through otg_vbus_drv and naming conversion followed
as per schematic.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:36 +01:00
Jagan Teki
fd0d7f9345 ARM: dts: rockchip: Add usb host for rk3288-vyasa
Add usb host support for rk3288-vyasa, board support hub power
through phy_pwr_en and usb2 host power through usb2_pwr_en and
naming conversion followed as per schematic.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:36 +01:00
Jagan Teki
7d07b83618 rockchip: rk3288-vyasa: defconfig: Enable gmac support
Enable gmac support for rk3288-vyasa board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:36 +01:00
Jagan Teki
0d3193415d ARM: dts: rockchip: Add gmac support for rk3288-vyasa board
Sync gmac dts node from Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:36 +01:00
Jagan Teki
ad6c965529 ARM: dts: rockchip: Add regulators for rk3288-vyasa
Add supporting regulators for rk3288-vyasa board, dc12_vbat is
parent regulatorand followed regulators as are child regulators.
regulator naming conversion followed as per schematic for better
readability and easy for identification.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Jagan Teki
58b3f26fd7 ARM: dts: rockchip: rk3288-vyasa: Use vmmc-supply from PMIC
rk808, SWITCH_REG1 has configured for sdmmc regulator as vcc_sd,
so use the same by renaming vcc33_sd to vcc_sd(as per schematic)
and drop explicit regulator definition from root.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Jagan Teki
764a94d90c ARM: dts: rockchip: rk3288-vyasa: Remove vdd_log from rk808, DCDC_REG1
vdd_log, never used on DCDC_REG1 of rk808 from latest schematic so
remove the same and update the regulator-name as 'vdd_arm' to sync
with existing rk3288 board dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Jagan Teki
d11455f56a ARM: dts: rockchip: Sync rk3288-vyasa dts from Linux
Sync rk3288-vyasa board dts from Linux for proper updates and maintenance
- rk3288-vyasa.dts: Similar to Linux dts
- rk3288-vyasa-u-boot.dtsi: u-boot dts changes

Also updated MAINTAINERS for these dts files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Klaus Goger
0c8e0b319f rockchip: add text_offset to kernel_addr_r on aarch64 platforms
Booting a aarch64 Linux kernel requires the image to be placed
text_offset bytes from a 2MB aligned address.
See https://www.kernel.org/doc/Documentation/arm64/booting.txt

booti_setup() takes care about this alignment and will relocate the
image if not properly aligned with memmove(). This can require up
to double the size of the loaded image and therefore accidentally
overwrite content placed there (i.e ramdisk_addr_r) for large kernel
images.

By adding text_offset to the default kernel_addr_r we can prevent that
from happening for kernels larger 18MB and also save a few cycles.

We can assume a text_offset of 0x80000 for most cases, all others will be
handled by booti_setup() anyway.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Kever Yang
f9326ec318 rockchip: pwm: convert to use live dt
use live dt api to get base addr

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Kever Yang
bbfef40f92 rockchip: clk: rk1108: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Kever Yang
08516431cf rockchip: clk: rk3328: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Kever Yang
995cde1f9c rockchip: clk: rk3288: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:35 +01:00
Kever Yang
99b8553cb8 rockchip: clk: rk322x: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:34 +01:00
Kever Yang
aca456471f rockchip: clk: rk3188: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:34 +01:00
Kever Yang
7ae028b669 rockchip: clk: rk3036: convert to use live dt
Use live dt api to get cru base addr.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-13 18:12:34 +01:00
Stefan Mavrodiev
d682cff440 sunxi: Add A20-SOM204-EVB-eMMC board
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 22:40:35 +05:30
Stefan Mavrodiev
8dd6497d9c sunxi: Add A20-SOM204-EVB board
This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules.

Base features of A20-SOM204 board includes:
	* 1GB DDR3 RAM
	* AXP209 PMU
	* KSZ9031 Gigabit PHY
	* AT24C16 EEPROM
	* Status LED
	* LCD connector
	* GPIO connector

There will be variants with the following options:
	* Second LAN8710A Megabit PHY
	* 16MB SPI Flash memory
	* eMMC card
	* ATECC508 crypto device

The EVB board has:
	* Debug UART
	* MicroSD card connector
	* USB-OTG connector
	* Two USB host
	* RTL8723BS WiFi/BT combo
	* IrDA transceiver/receiver
	* HDMI connector
	* VGA connector
	* Megabit ethernet transceiver
	* Gigabit ethernet transceiver
	* SATA connector
	* CAN driver
	* CSI camera
	* MIC and HP connectors
	* PCIe x4 connector
	* USB3 connector
	* Two UEXT connectors
	* Two user LEDs

Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.

This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 22:38:58 +05:30
Stefan Mavrodiev
b30c419040 Move CONFIG_PHY_ADDR to Kconfig
CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).

Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.

After the implemention, moveconfig was run. The issues are:
	- edb9315a	- CONFIG_PHYLIB is not enabled. Entry is
			  deleted.

	- ds414		- CONFIG_PHYLIB is in incompatible format:
			  { 0x1, 0x0 }. This entry is also deleted.

	- devkit3250	- The PHY_ADDR is in hex format (0x1F).
			  Manually CONFIG_PHY_ADDR=31 is added in
			  the defconfig.

After the changes the suspicious defconfigs passes building.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 22:36:33 +05:30
Samuel Holland
2d53018a0e net: sun8i_emac: Fix PHY initialization
The previous code tried to update the PHY parameters without waiting for
autonegotiation to complete. This caused wrong values to be written to
the EMAC in sun8i_adjust_link(). As a result, any commands that called
eth_start() before autonegotiation completed would find the network
nonfunctional. Fix this by using the correct function to start up the
PHY.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 21:16:51 +05:30
Tuomas Tynkkynen
b0b0d22f1a ARM: sunxi: Build u-boot-sunxi-with-spl.bin on ARM64 as well
In README.sunxi64 we tell the user how to optionally create
u-boot-sunxi-with-spl.bin by manually running cat. Instead, have the
build system create the file automatically just like it does for 32-bit
sunxi boards.

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 20:36:51 +05:30
Tuomas Tynkkynen
155b116907 ARM: sunxi: Move u-boot-sunxi-with-spl.bin rule to Makefile
We're going to need this logic for 64-bit builds as well, so move it
out from under arch/arm/cpu/armv7.

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 20:36:16 +05:30
Heinrich Schuchardt
8be4e61d01 mmc: sunxi: support cd-inverted
With CONFIG_DM_MMC the BananaPi does not detect SD cards.

The sunxi device trees use the cd-inverted property to indicate that
the card detect is inverted.

This property is documented in Linux kernel devicetree/bindings/mmc/mmc.txt
The property is not marked as deprecated.

A similar patch was posted by Tuomas but is in status "Changes Requested".
https://patchwork.ozlabs.org/patch/850377/

This patch is a stripped down version of his patch.

Suggested-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-13 20:12:31 +05:30
Chen-Yu Tsai
1bcfba537e sunxi: Add reg property for USB OTG node in sun8i-a83t.dtsi
When the OTG node was added, its reg property for its address space was
missing. With commit f4f9896ac3 ("musb: sunxi: Use base address from
device tree"), the OTG controller's address is derived from the device
tree exclusively. The missing property results in U-boot crashing when
MUSB is initialized.

Fixes: b0bea66789 ("sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2018-03-13 20:03:45 +05:30
Andre Przywara
47952b8e42 sunxi: Pine64: temporarily remove extra Pine64 non-plus DT
With the merge of the new u-boot.itb size check now the build for
pine64_plus_defconfig breaks, as this file gets too large:
=============
u-boot.itb exceeds file size limit:
  limit:  516096 bytes
  actual: 521852 bytes
  excess: 5756 bytes
make: *** [u-boot.itb] Error 1
=============
One easily fixable reason is that we actually have two .dtbs in our FIT
image, one for the regular Pine64+ board, and one for the non-plus version.
The only difference U-Boot cares about is the 100Mbit Ethernet PHY used
on the non-plus version, however Ethernet isn't enabled in the non-plus
DT anyway.
So we could avoid the non-plus special handling, and remove that extra
.dtb from the FIT image, which saves a few KBs and brings us back below the
limit. The Pine64 would boot with a Pine64+ .dtb, and would fail to
enable Ethernet. Given that it didn't work in the first place, this is not
a regression.
Once we switch to a non-MMC environment, we can bring this back, then
with a proper .dtb and hopefully working Ethernet.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-13 20:03:45 +05:30
Jagan Teki
c2a7a7ef86 arm: sunxi: Move spl spi sunxi code to mach-sunxi
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.

And also renamed the file according to kconfig which resembles
proper name.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Jagan Teki
8480792287 spi: omap3: Skip set_mode, set_speed from claim
set_mode, set_seed functions has separate function pointers
in dm_spi_ops, so use them in relevent one instead of
calling from claim_bus.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Jagan Teki
15927aef02 spi: atcspi200: Drop non-dm code
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig
already enabled DM_SPI, so non-dm code make no use
of it hence droped.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Tom Rini
f95ab1fb6e Prepare v2018.03
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-13 08:02:19 -04:00