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clk: clk_stm32h7: Fix prescaler for Domain 3
d1cfgr register was used to calculate the domain 3 prescaler value instead of d3cfgr. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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parent
b43679482b
commit
09b335a675
1 changed files with 4 additions and 3 deletions
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@ -635,7 +635,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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struct stm32_rcc_regs *regs = priv->rcc_base;
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ulong sysclk = 0;
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u32 gate_offset;
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u32 d1cfgr;
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u32 d1cfgr, d3cfgr;
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/* prescaler table lookups for clock computation */
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u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
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u8 source, idx;
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@ -712,9 +712,10 @@ static ulong stm32_clk_get_rate(struct clk *clk)
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break;
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case RCC_APB4ENR:
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if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
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d3cfgr = readl(®s->d3cfgr);
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if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
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/* get D3 domain APB4 prescaler */
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idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
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idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
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RCC_D3CFGR_D3PPRE_SHIFT;
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sysclk = sysclk / prescaler_table[idx];
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}
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