Commit graph

455 commits

Author SHA1 Message Date
Peter Tyser
62c3ae7c6e Standardize command usage messages with cmd_usage()
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-01-28 08:43:45 +01:00
Dirk Eibach
3943d2ff6c ppc4xx: Improve DDR autodetect
Added support for a second memory bank to DDR autodetection for 440
platforms.
Made hardcoded values configurable.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-01-26 10:13:11 +01:00
Wolfgang Denk
455ae7e87f Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16 01:02:17 +01:00
Timur Tabi
ecf5f077c8 i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-15 23:46:21 +01:00
Trent Piepho
5e3ab68e9a Section name should be ".data", not "data"
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-09 00:48:41 +01:00
Peter Tyser
561858ee7d Update U-Boot's build timestamp on every compile
Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-06 23:36:43 +01:00
Dave Mitchell
ddf45cc758 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 11:02:04 +01:00
Dave Mitchell
b14ca4b61a ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:33 +01:00
Stefan Roese
25fb4eaaea ppc4xx: Clear all potentially pending exceptions in MCSR
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().

Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-20 11:48:53 +01:00
Ben Warren
25a859066b Moved initialization of PPC4xx EMAC to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:05 -08:00
Ben Warren
4d03a4e20e Moved PPC4xx EMAC driver to drivers/net
Also changed path in all linker scripts that reference this driver

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ben Warren
96e21f86e8 Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-11-09 21:38:04 -08:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Adam Graham
c9c11d751e ppc4xx: Add routine to retrieve CPU number
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's.  Default behavior
is the existing single CPU print output.  Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:56 +02:00
Adam Graham
59217bae40 ppc4xx: Add static support for 44x IBM SDRAM Controller
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:51 +02:00
Wolfgang Denk
8ed44d91c8 Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:39 +02:00
Markus Klotzbuecher
50bd0057ba Merge git://git.denx.de/u-boot into x1
Conflicts:

	drivers/usb/usb_ohci.c
2008-10-21 09:18:01 +02:00
Wolfgang Denk
f82642e338 Merge 'next' branch
Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-18 21:59:44 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Yuri Tikhonov
bf29e0ea0a ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-17 13:02:42 +02:00
Remy Bohmer
9dbc366744 The PIPE_INTERRUPT flag is used wrong
At a lot of places in the code the PIPE_INTERRUPT flags and friends
are used wrong. The wrong bits are compared to this flag resulting
in wrong conditions. Also there are macros that should be used for
PIPE_* flags.
This patch tries to fix them all, however, I was not able to test the
changes, because I do not have any of these boards.

Review required!

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
2008-10-14 16:43:06 +02:00
Adam Graham
f8a00dea84 ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-08 11:36:23 +02:00
Stefan Roese
023824549a Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"
This reverts commit 3eec160a3a.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-22 11:06:50 +02:00
Victor Gallardo
3eec160a3a ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-16 20:16:31 +02:00
Stefan Roese
7bf5ecfa50 ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-12 07:12:33 +02:00
Stefan Roese
f071f01fd0 ppc4xx: Remove CONFIG_CS8952_PHY define
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:56 +02:00
Stefan Roese
6ca8646c18 ppc4xx: Fix compilation warning for PIP405
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:51 +02:00
Stefan Roese
725b53ac61 ppc4xx: Fix compilation warning for canyonlands & glacier
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:46 +02:00
Victor Gallardo
78d7823689 ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:21:16 +02:00
Adam Graham
f6b6c45840 ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:04:16 +02:00
Adam Graham
075d0b81e8 ppc4xx: IBM Memory Controller DDR autocalibration routines
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).

Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B".  DDR autocalibration Method_A scans the full range
of possible PPC4xx  SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B.  Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.

The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1)  SDRAM0_RQDC.[RQFD]
2)  SDRAM0_RFDC.[RFFD]

This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:

1)  SDRAM0_WRDTR.[WDTR]
2)  SDRAM0_CLKTR.[CKTR]
3)  SDRAM0_RQDC.[RQFD]
4)  SDRAM0_RFDC.[RFFD]

and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:03:44 +02:00
Stefan Roese
c2b4b2e481 ppc4xx/NAND: Add select_chip function to 4xx NDFC driver
This function is needed for the new NAND infrastructure. We only need
a dummy implementation though for the NDFC.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-30 11:24:54 +02:00
Wolfgang Ocker
52aef8f9ba ppc4xx: NAND configuration
Made NAND bank configuration setting a config variable.

Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-29 10:21:31 +02:00
Victor Gallardo
5bc542a593 ppc4xx: fix UIC external_interrupt hang on UIC0
This patch fixes a UIC external_interrupt hang if critical or non-critical
interrupt is set at the same time as a normal interrupt is set on UIC0.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-29 10:13:59 +02:00
Prodyut Hazarika
04737d5ffd ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory Controller
Removed Magic numbers from Initialization preload registers
Tested with Kilauea, Glacier, Canyonlands and Katmai boards
About 5-7% improvement seen for LMBench memtests

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-29 10:01:36 +02:00
Tirumala R Marri
5d4b3d2b31 ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fix
During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-22 10:31:41 +02:00
Stefan Roese
f556483734 ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patch
This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:

- Rework memory-queue and PLB arbiter optimization code, that the
  local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
  of XXX+ 0x01). This was not introduced by Prodyut, just a
  copy-paste problem.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 11:05:03 +02:00
Prodyut Hazarika
079589bcfb ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 10:31:16 +02:00
Kumar Gala
ba37aa0328 fdt: rework fdt_fixup_ethernet() to use env instead of bd_t
Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.

This makes the code a bit more flexible to the number of ethernet
interfaces.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-21 02:07:43 +02:00
Wolfgang Denk
2fd0aad443 Merge branch 'Makefile' of git://git.denx.de/u-boot-arm 2008-08-13 23:23:13 +02:00
Stefan Roese
5a7ddf4e1f Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-08-13 06:47:12 +02:00
Jean-Christophe PLAGNIOL-VILLARD
cc4a0ceeac drivers/mtd/nand: Move conditional compilation to Makefile
rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13 01:40:43 +02:00
Stefan Roese
3df2ece0f0 NAND: Update 4xx NDFC driver to match updated nand subsystem
This patch changes the 4xx NAND driver ndfc.c to match the new
infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Tested successfully on AMCC Sequoia and Bamboo.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-12 11:31:23 -05:00
William Juul
5e1dae5c3d Fixing coding style issues
- Fixing leading white spaces
 - Fixing indentation where 4 spaces are used instead of tab
 - Removing C++ comments (//), wherever I introduced them

Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:17 -05:00
William Juul
cfa460adfd Update MTD to that of Linux 2.6.22.1
A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.

This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.

MAKEALL ppc/arm has some issues:
 * DOC/OneNand/nand_spl is not building (I have not tried porting
   these parts, and since I do not have any HW and I am not familiar
   with this code/HW I think its best left to someone else.)

Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
 cpu/ppc4xx/ndfc.c
 cpu/arm926ejs/davinci/nand.c
 board/delta/nand.c
 board/zylonite/nand.c

Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Stig Olsen <stig.olsen@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:15 -05:00
Stefan Roese
f2302d4430 Fix merge problems
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-06 14:05:38 +02:00
Stefan Roese
66fe183b1d ppc4xx: Fix incorrect MODTx setup for some DIMM configurations
This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-18 15:57:23 +02:00
Stefan Roese
60204d06ed ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-18 12:31:25 +02:00