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075d0b81e8
Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> |
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.. | ||
4xx_enet.c | ||
4xx_ibm_ddr2_autocalib.c | ||
4xx_pci.c | ||
4xx_pcie.c | ||
4xx_uart.c | ||
40x_spd_sdram.c | ||
44x_spd_ddr.c | ||
44x_spd_ddr2.c | ||
bedbug_405.c | ||
cache.S | ||
commproc.c | ||
config.mk | ||
cpu.c | ||
cpu_init.c | ||
dcr.S | ||
denali_data_eye.c | ||
denali_spd_ddr2.c | ||
ecc.c | ||
ecc.h | ||
fdt.c | ||
gpio.c | ||
i2c.c | ||
interrupts.c | ||
iop480_uart.c | ||
kgdb.S | ||
Makefile | ||
miiphy.c | ||
ndfc.c | ||
resetvec.S | ||
sdram.c | ||
sdram.h | ||
speed.c | ||
start.S | ||
tlb.c | ||
traps.c | ||
uic.c | ||
usb.c | ||
usb_ohci.c | ||
usb_ohci.h | ||
usbdev.c | ||
usbdev.h | ||
xilinx_irq.c |