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ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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3 changed files with 37 additions and 5 deletions
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@ -374,3 +374,34 @@ int post_hotkeys_pressed(void)
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return 0; /* No hotkeys supported */
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}
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#endif /* CONFIG_POST */
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
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/*
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* This is for quicker auto calibration boot up once WRDTR and CLKTR
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* values for the kilauea board were determined and are therefore known.
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*
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* Use these scan options for PLB bus greater than or equal 200MHz
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* else use the defaults. These options are known to return a cycle
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* delay of T2 or better with a 200MHz PLB bus. Scanning the
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* full list of WDTR/CLKTR should work, but currently it does not.
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* HW team is investigating.
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*/
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/* List of (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CLKP]) pairs to try */
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struct sdram_timing quick_scan_options[] = {
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{0, 3}, {1, 1}, {1, 2}, {1, 3},
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{2, 1}, {2, 2}, {2, 3}, {3, 1},
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{3, 2}, {4, 1}, {-1, -1}
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};
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ulong ddr_scan_option(ulong default_val)
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{
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PPC4xx_SYS_INFO board_cfg;
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get_sys_info(&board_cfg);
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if (board_cfg.freqPLB >= 200000000)
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return (ulong)(quick_scan_options);
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else
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return (ulong)default_val;
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}
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#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
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@ -79,11 +79,6 @@ struct ddrautocal {
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u32 flags;
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};
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struct sdram_timing {
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u32 wrdtr;
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u32 clktr;
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};
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struct sdram_timing_clks {
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u32 wrdtr;
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u32 clktr;
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@ -1403,6 +1403,12 @@
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#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
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#ifndef __ASSEMBLY__
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struct sdram_timing {
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u32 wrdtr;
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u32 clktr;
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};
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/*
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* Prototypes
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*/
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