Commit graph

56443 commits

Author SHA1 Message Date
Simon Goldschmidt
9dc61aac2d arm: socfpga: gen5: reduce SPL pre-reloc malloc
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
aef44283ac arm: socfpga: imply/default common config options
This commit moves common config options used in all socfpga boards
to select/imply in Kconfig. This both cleans up the defconfig files
as well as makes future changes easier.

Options implied/defaulted for all sub-arches:
- SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS

Options implied/defaulted for implied for A10 & gen5:
- FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE

Options implied/defaulted for gen5:
- SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
4399e48deb arm: socfpga: put initial U-Boot stack into DDR
If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to
do that, too.

The reason to do so is that this way, U-Boot initial stack can be larger
than SPL initial stack. In situations where we want to save the SPL
in SRAM for next boot without reloading, this prevents overwriting the
SPL DTB in SRAM if U-Boot stack usage gets too high.

To achieve this, the malloc definition for a10 is moved up and sligthly
changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
798baf7ca3 arm: socfpga: fix comment about SPL memory layout
The comment about SPL memory layout for socfpga gen5 is outdated: the
initial malloc memory is now at the end of the SRAM, gd is below it
(see board_init_f_alloc_reserve).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
ac1ec53e26 configs: socfpga: socrates: enable rtc support
This enables DM_RTC and RTC_M41T62 to enable support for the rtc on the
socrates board.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
d1aa159d99 arm: socfpga: socrates: make rtc work
This patch makes the on-board RTC work on the socfpga_socrates board.
This rtc is present on the board, but it does not work (fails with a
timeout).

This patch adds a weak pull-up on the I2C0-SCL pin connected to the m41t82
RTC on this board. While the SDA line has a pull-up on the pcb, the pull-up
on the SCL line seems to be missing. To work around this, enable the
weak-pull-up feature on this pin.

After applying this patch, the rtc timeout is gone and the 'date' command
can access the rtc chip.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
4e829e9841 rtc: m41t62: add compatible for m41t82
This adds a compatible string for m41t82. This ensures that this driver
can be used for m41t82 in DM mode, too (asit was usable for this model in
non-DM mode before).

In addition, the HT bit has to be reset during probe, since the m41t82
chip sets it when entering battery standby mode.

This patch ensures this driver works on socfpga_socrates.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
36821b3f55 i2c: designware: fix reset handling on socfpga gen5
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort
as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide
reset-names).

The actual bug was to check 'if (&priv->reset_ctl)', which is never false.

While at it, convert the driver to use 'reset_get_bulk' instead of looking
at a specific named reset and also make it release the reset on driver
remove before starting the OS.

Fixes: 622597dee4 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
bbecfd4cf2 Revert "cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT"
This reverts commit 65a97e7fcf.

The 'eeprom' command has been converted to work with DM_I2C in a patch
submitted around the same time as this commit:
commit 0c07a9b407 ("eeprom: Add device model based I2C support to eeprom command")

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
4f25617758 eeprom: fix DM_I2C support without CONFIG_SYS_I2C_EEPROM_BUS
The current device model enabled eeprom code only works if
CONFIG_SYS_I2C_EEPROM_BUS is set.

This patch makes it work without that define so that the bus
number passed to 'eeprom_init' is used.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
a339f5249d socfpga: add Simon Goldschmidt as co-custodian
This updates MAINTAINERS and git-mailrc to add me as a
co-custodian for socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-24 17:01:38 +02:00
Tom Rini
3fbd2dce35 Merge branch '2019-04-22-master-imports'
- Add and enable brcmnand driver on a number of relevant platforms.
  Also add and enable LED drivers on more bcm platforms.
- Various ARMv8 fixes/improvements, including extending PSCI
  functionality.
- fs_loader improvments
- Various FIT/SPL improvements
- PCI bugfixes
- Poplar platform ethernet support
- MediaTek MMC improvements
- Android boot improvements
2019-04-24 09:04:23 -04:00
Eugeniu Rosca
74a7e0018a image: android: fix 'iminfo' typo
Fix below CP warning triggered by the 'iminfo' output in another patch:
WARNING: 'addrress' may be misspelled - perhaps 'address'?

Fixes: 4f1318b29c ("common: image: minimal android image iminfo support")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2019-04-24 07:27:32 -04:00
Eugeniu Rosca
829ceb2821 image: android: allow booting lz4-compressed kernels
According to Android image format [1], kernel image resides at 1 page
offset from the boot image address. Grab the magic number from there
and allow U-Boot to handle LZ4-compressed KNL binaries instead of
hardcoding compression type to IH_COMP_NONE. Other compression types,
if needed, can be added later.

Tested on H3ULCB-KF using the image detailed in [2].

[1] Excerpt from include/android_image.h
    +-----------------+
    | boot header     | 1 page
    +-----------------+
    | kernel          | n pages
    +-----------------+
    | ramdisk         | m pages
    +-----------------+
    | second stage    | o pages
    +-----------------+

[2] => iminfo 4c000000
    ## Checking Image at 4c000000 ...
    Android image found
    kernel size:      85b9d1
    kernel address:   48080000
    ramdisk size:     54ddbc
    ramdisk addrress: 4a180000
    second size:      0
    second address:   48000800
    tags address:     48000100
    page size:        800
    os_version:       1200012a (ver: 0.9.0, level: 2018.10)
    name:
    cmdline:          buildvariant=userdebug

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-04-24 07:27:32 -04:00
Heinrich Schuchardt
0efe2b8f9e test: env: Enable env unit tests by default
If CONFIG_UNIT_TEST is enabled we should enable the individual tests by
default to ensure good test coverage.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-04-24 07:27:28 -04:00
Lars Povlsen
25c07c72fd ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.

When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-04-23 17:57:28 -04:00
Trent Piepho
b4353b3713 bootm: Simplying cache flush code
The cache flush of the kernel load area needs to be aligned outward to
the DMA cache alignment.  The operations are simpler if we think of this
as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and
aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find
the length of the flushed region by subtracting the former from the
latter.

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:27 -04:00
Andreas Dannenberg
4c6be01c27 malloc: Fix memalign not honoring alignment prior to full malloc init
When using memalign() in a scenario where U-Boot is configured for full
malloc support with simple malloc not explicitly enabled and before the
full malloc support is initialized, a memory block is being allocated
and returned without the alignment parameter getting honored.

Fix this issue by replacing the existing memalign pre-full malloc init
logic with a call to memalign_simple() this way ensuring proper alignment
of the returned memory block.

Fixes: ee038c58d5 ("malloc: Use malloc simple before malloc is fully initialized in memalign()")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-23 17:57:27 -04:00
Stefan Roese
443b3ce5cf spl: spl_nand.c: Add NAND loading message
This patch adds a short message to the SPL NAND loader, which displays
the source and destinations addresses including the size of the
loaded image, like this:

U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100)
Trying to boot from NAND
Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000

I find this message quite helpful - hopefully others do so as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:27 -04:00
Fabien Parent
def2fc05f6 ARM: MediaTek: Add support for MT8516 SoC
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
6fdb50c098 pinctrl: add driver for MT8516
Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
cd52c3253a clk: mediatek: add driver for MT8516
Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
[trini: Redo whitespace]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
fe913a8bb6 clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
b5096f1b6d mmc: mtk-sd: fix configuration option check
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.

This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
a93326681d mmc: mtk-sd: add support for MT8516
Add config for handling MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
ba077e5f74 mmc: mtk-sd: add source_cg clock support
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Shawn Guo
7c798a11d4 poplar: enable Ethernet driver support
The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed.  With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:25 -04:00
Shawn Guo
1d5b5d2f8f net: add higmacv300 Ethernet driver for HiSilicon platform
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Shawn Guo
f5e6c168c1 reset: add reset driver for HiSilicon platform
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Shawn Guo
f5ed7481e7 reset: add polarity field into struct reset_ctl
Some reset controllers support different polarities for reset operation,
so let's add a polarity field into struct reset_ctl.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Thierry Reding
aec4298ccb pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS
If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Thierry Reding
d94d9aa675 pci: Add boundary check for hose->regions
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Adam Ford
248b873541 ARM: da850evm: Remove legacy MMC code
With the migration to DM in SPL and the DT support, the
old legacy code is no longer neaded, so this patch removes it

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-23 17:57:23 -04:00
Philippe Reynes
d6ce4c054a bcm963158: enable led support
Enable the led support in the configuration
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:23 -04:00
Philippe Reynes
4ae0542de7 dt: bcm963158: enable led controller
Enable the led controller in the device tree
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
cfbb03be1c dt: bcm63158: add led controller
Add the led controller in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
4ac59e3381 led: bcm6858: allow to use this driver on ARCH_963158
Allow the led bcm6858 driver to be used on bcm63158.
They have the same led controller.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
102b2317d8 bcm968580xref: enable led support
Enable the led support in the configuration
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
9689921921 dt: bcm968580xref: enable led controller
Enable the led controller in the device tree
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:14 -04:00
Philippe Reynes
7526582441 dt: bcm6858: add led controller
Add the led controller in the bcm6858 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 18:13:24 -04:00
Philippe Reynes
d00c6a2d56 led: add initial support for bcm6858
The driver add the support of the led IP on bcm6858.
This led IP can drive up to 32 leds, and can handle
blinking.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-22 18:13:24 -04:00
Ibai Erkiaga
98ffbb78e1 arm: arm64 32bit address relocation
Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the addressing to 32bit PC-relative. This feature is
specially interesting if U-Boot is build without optimiation (-O0) as
the text section is increased significativelly.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
2019-04-22 18:13:24 -04:00
Marek Vasut
aa2e9c9e80 travis: Add srecord package
At least MIPS Boston currently uses srec_cat tool to fiddle with
srecords. There will be other platforms coming, so install the
tool to prevent build problems.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
2019-04-22 18:13:23 -04:00
Stefano Babic
bdaa73a5b3 Add target to generate initial environment
The initial environment is linked to the u-boot binary. Modifying the
environment from User Space with the env tools requires that the tools
are always built together with the bootloader to be sure that they
contain the initial environment in case no environment is stored into
persistent storage or when a board boots with just the default
environment. This makes difficult for distros to provide a general
package to access the environment. A simpler way is if the tools are
generic for all boards and a configuration file is given to provide the
initial environment.

The patch just generates the initial environment by extracting it from
the compiled object. This file can then be used for tools in user space
to initialize the environment.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-04-22 18:13:23 -04:00
Marek Vasut
792dd57091 spl: ymodem: Add support for loading full fitImages
Add support for loading fully featured fitImages over YModem in SPL.
This is useful when various advanced features of full fitImages are
needed in SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2019-04-22 18:13:23 -04:00
Peter Ujfalusi
35c7527eb9 fit: load all fragments from the extra configurations
Currently only the first fdt is loaded from the extra configuration of
FIT image.
If the configuration have multiple fdt, load them all as well.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-22 18:13:23 -04:00
Tien Fong Chee
c1ef736e3d misc: fs_loader: Replace label with DT phandle
In previously label which will be expanded to the node's full path was
used, and now replacing label with most commonly used DT phandle. The
codes were changed accordingly to the use of DT phandle and supporting
multiple instances.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-22 18:13:22 -04:00
Ibai Erkiaga
1721b82c1f arm: fix hvc call
HVC call makes use of 6 mandatory arguments rather than 7 in the same way
as SMC calls. The 7th argument is optional (Client ID) for both HVC and
SMC but is implemented as 16-bit parameter and register R7 or W7. The aim
of this patch is just fix compilation error due to an invalid asm code in
the HVC call so that's why the 7th argument is removed.

The issue does not report any error in a normal build as hvc_call is not
used at all and is optimized by the compiler. Using -O0 triggers the
error so the patch is intended to fix issues on a ongoing effor to build
U-Boot with -O0.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
2019-04-22 18:13:22 -04:00
Shawn Guo
5e218862b7 Support boot Android image without address on bootm command
It works perfectly fine to boot an Android boot.img with bootm command
followed by an explicit address argument that holds the image.  But if
we have boot.img downloaded into default 'loadaddr', and then boot it
using bootm command without the address argument, we will run into
problem, because U-Boot fails to find ramdisk and fdt (second area) in
boot.img.

The current Android image support assumes there is always an address
argument on bootm command.  However just like booting any other images,
'loadaddr' should be used when address argument is missing from bootm
command.  It patches boot_get_ramdisk() and boot_get_fdt() a bit to
support this quite common usage of bootm command for Android image.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-22 18:13:22 -04:00
Tien Fong Chee
3695ea5deb cmd: ximg.c: Add support for getting external data address and length
This function supports getting both data address and length for
existing FIT subimage and FIT external data.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-22 18:13:22 -04:00