Add reset_sata() to the sata driver interface and implement it
for dwc_ahsata. This function cleans up after sata_init(), and
therefore accepts a device number like sata_init() does.
A dummy implementation is provided for the rest of the drivers.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible
and safer than DIV_ROUND.
For example,
foo = DIV_ROUND_CLOSEST(x, y++)
works expectedly, but
foo = DIV_ROUND(x, y++)
does not. (y is incremented twice.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Rename some defines containing FAT in their name to be filesystem generic:
MMCSD_MODE_FAT => MMCSD_MODE_FS
CONFIG_SPL_FAT_LOAD_ARGS_NAME => CONFIG_SPL_FS_LOAD_ARGS_NAME
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME => CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION => CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().
Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Fixes commit a0a37183bd
ARM: omap: merge GPMC initialization code for all platform
1) NAND device are not directly memory-mapped to CPU address-space, they are
indirectly accessed via following GPMC registers:
- GPMC_NAND_COMMAND_x
- GPMC_NAND_ADDRESS_x
- GPMC_NAND_DATA_x
Therefore from CPU's point of view, NAND address-map can be limited to just
above register addresses. But GPMC chip-select address-map can be configured
in granularity of 16MB only.
So this patch uses GPMC_SIZE_16M for all NAND devices.
2) NOR device are directly memory-mapped to CPU address-space, so its
address-map size depends on actual addressable region in NOR FLASH device.
So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
size configuration.
Signed-off-by: Pekon Gupta <pekon@ti.com>
The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:
NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting
As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.
Tested on TAO3530 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
gpmc timeout is disabled and the reset counter
is set to 0. However, if later a driver activates
the timeout setting the reset to a valid value,
the old reset value with zero is still valid
for the first access. In fact, the timeout block
loads the reset counter after a successful access.
Found on a am335x board with a FPGA connected
to the GPMC bus together with the NAND.
When the FPGA driver in kernel activates
the timeout, the system hangs at the first access
by the NAND driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set
for GPMC on chip select #0---size is 0. In this case, the GPMC
configuration should be reset but not enabled. Enabling causes the
Gumstix DuoVero board to hang when entering Linux.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
[trini: Switch to testing base as GPMC_SIZE_256M is 0x0]
Signed-off-by: Tom Rini <trini@ti.com>
Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined.
This speeds up the Beaglebone Black boot considerable.
(Tested only on Beaglebone Black with SD card boot)
Signed-off-by: Simon Glass <sjg@chromium.org>
Last section of DMM is used for trapping tiler unmapped sections.
Corresponding trap_size should be deducted from total SDRAM size
only if trap section is overlapping with available SDRAM
based on DMM sections. Fixing the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The omap_hw_init_context function (and assorted helpers) is the same for
all OMAP-derived parts as when CHSETTINGS are used, that's the same and
our DDR base is also always the same. In order to make this common we
simply need to update the names of the define for DDR address space
which is also common.
Cc: Sricharan R. <r.sricharan@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>
GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
- Ethernet Devices like LAN9220
Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.
Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.c
However, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: arch/arm/include/asm/arch-omap3/mem.h
OMAP4: arch/arm/include/asm/arch-omap4/mem.h
OMAP4: arch/arm/include/asm/arch-omap5/mem.h
Also, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
CONFIG_NAND: initialize GPMC for NAND device
CONFIG_NOR: initialize GPMC for NOR device
CONFIG_ONENAND: initialize GPMC for ONENAND device
Signed-off-by: Pekon Gupta <pekon@ti.com>
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini <trini@ti.com>
We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad)
read support as well. This means we can be given one of two boot device
values, but don't care which it is, so perform a fixup on the QSPI_4
value. We add a qspiboot build target to better show how you would use
QSPI as a boot device in deployment. When we boot from QSPI, we can
check the environment for 'boot_os' to control Falcon Mode.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
TI platforms such as OMAP5uevm, PandaBoard, use equivalent
logic to generate fake USB MAC address from device unique DIE ID.
Consolidate this to a generic location such that other TI platforms such
as BeagleBoard-XM can also use the same.
NOTE: at this point in time, I dont yet see a need for a generic dummy
ethernet MAC address creation function, but if there is a need in the
future, this can be further abstracted out.
Signed-off-by: Nishanth Menon <nm@ti.com>
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
This prevents references to _end from generating absolute
relocation records.
This change is binary invariant for ARM targets.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
arch/arm/cpu/armv7/omap-common/config.mk is never included
because "omap-common" is not SoC name.
If we want to add OMAP-specific compiler flags,
they must be added to omap3/config.mk, omap4/config.mk, omap5/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
- When CONFIG_DISPLAY_CPUINFO is not enabled,
print_cpuinfo() should be defined as an empty function
in a header, include/common.h
- Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif
from caller, common/board_f.c and arch/arm/lib/board.c
- Remove redundant prototypes in arch/arm/lib/board.c,
arch/arm/include/asm/arch-am33x/sys_proto.h and
board/nokia/rx51/rx51.h, keeping the one in include/common.h
- Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition
where it is missing
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Add the SATA boot support for OMAP5 and dra7xx.
Renamed the omap_sata_init to the common init_sata(int dev)
for commonality in with sata stack.
Added the ROM boot device ID for SATA.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some
additional features of the eMMC boot partitions. Add support for being
told that we have booted from one of these partitions to the spl
framework and implement this on TI OMAP/related.
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ABB code uses LDELAY but does not include the header that provides its
definition.
Include the header.
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Nishanth Menon <nm@ti.com>
When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include
adapter information, as we use i2c during SPL. However, the regex used
also means we included commands that may have been built. On omap5_uevm
this leads to a failure as we include the command from the do_tca642x
command, and fail to link. The fix is to restrict our regex to only the
i2c list parts.
Signed-off-by: Tom Rini <trini@ti.com>
- add omap24xx driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Tested on the am335x based siemens boards rut, dxr2 and pxm2
posted here:
http://patchwork.ozlabs.org/patch/263211/
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tom Rini <trini@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Michael Jones <michael.jones@matrix-vision.de>
Cc: Raphael Assenat <raph@8d.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefano Babic <sbabic@denx.de>
Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.h
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
board/compulab/common/Makefile
board/udoo/Makefile
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h
Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.
Boot tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
We need to allow for a further call-out in spl_board_init. Call this
am33xx_spl_board_init and add a __weak version. This function may be
used to scale the MPU frequency up, depending on board needs.
Signed-off-by: Tom Rini <trini@ti.com>
Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon"
(f40107345c)
changed sequence to set final DDR PHY config register value at the beginning.
Looks like it was made by mistake and should be reverted.
Signed-off-by: Taras Kondratiuk <taras@ti.com>
