Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.
Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
While working on an LX2160 based board and updating to latest mainline
I noticed problems using the HW accelerated hash functions on this
platform, when trying to boot a FIT Kernel image. Here the resulting
error message:
Using 'conf-freescale_lx2160a.dtb' configuration
Trying 'kernel-1' kernel subimage
Verifying Hash Integrity ... sha256Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty
error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
ERROR: can't get kernel image!
Testing and checking with Gaurav Jain from NXP has revealed, that this
alignment check is not necessary here at all. So let's remove this
check completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gaurav Jain <gaurav.jain@nxp.com>
Cc: dullfire@yahoo.com
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Clean up in ubiload script. Unmount UBIFS from which kernel image was
loaded and detach UBI on which the UBIFS is located, otherwise message
similar to the following is printed just before booting kernel:
Removing MTD device #7 (rootfs) with use count 1
Error when deleting partition "rootfs" (-16)
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This new MMC sample select value is obtained from running
tests on multiple Stratix 10 boards and proven working.
Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(),
where the IP clock are initially disabled. Drop the second disabling of
clock to prevent clock enable/disable imbalance reported by clock core:
"
clk qspi_root_clk already disabled
"
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
There is no wait_dat0 mmc ops, causing operations waiting for data
line state change (e.g mmc_switch_voltage) to fallback to a 250ms
active delay. mmc_ops still used when DM_MMC is not enabled, which
is often the case for SPL. The result can be unexpectly long SPL
boot time.
This change adds support for wait_dat0() mmc operation.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
On eMMC device, the erase_grp_size > 1 so the address and size for the
erase block command in env/mmc.c can be unaligned on erase group size and
some strange trace occurs and the result is not guarantee by MMC devices.
The SD-Card behavior doesn't change as erase_grp_size = 1 for SD-Card.
For example, on eMMC present on STM32MP15C-EV1 and before the patch:
STM32MP> env erase
Erasing Environment on MMC...
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x27ff
16 blocks erased: OK
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x23ff
16 blocks erased: OK
OK
After this patch:
STM32MP> env erase
Erasing Environment on MMC...
1024 blocks erased at 0x2000: OK
1024 blocks erased at 0x2000: OK
OK
Here the 2 copies of U-Boot environment are in the same devices Erase
group: it is erased twice.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.
for example:
- start = 0x2000 - 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x27ff
But no issue when the end address is not aligned, for example
- start = 0x2000 - 2 * 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x23ff
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Mark wdog1/pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,
The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace
CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop
CONFIG_SPL_ABORT_ON_RAW_IMAGE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
Since these boards has CONFIG_DM_SERIAL and/or CONFIG_SPL_DM_SERIAL,
the legacy macro no need to be defined.
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Upstream commit 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
HSIOMIX clock") added usb_core_ref for USB Controller but never set it
to be used as a clock source, using rather "osc_32k" instead.
This produces following boot log message:
"clk_register: failed to get osc_32k device (parent of usb_root_clk)"
Fix the USB controller clock source by using usb_core_ref instead of
osc_32k.
Fixes: 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Root clock name contained underscore, which does not match to the actual
clock name.
Correct the name to match what is present in the FDT.
Fixes: 87f958810f ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
systemd prints its messages on the last console= statement that it finds
in the kernel arguments. The current ordering sends the systemd messages
to tty1, by default this is the display.
Ensure that systemd sends its messages to the default UART, reorder the
console= statements accordingly.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Since SoMs revision 1.9 the ar8035 phy has been replaced by adin1300.
Enable the driver so that the new SoMs have functional networking.
Signed-off-by: Josua Mayer <josua@solid-run.com>
SoM revision 1.9 has replaced the ar8035 phy address 0 with an adin1300
at address 1. Because early SoMs had a hardware flaw, the ar8035 can
also appear at address 4 - making it a total of 3 phy nodes in the DTB.
To avoid confusing Linux with probe errors, fixup the dtb to only enable
the phy node that is detected at runtime.
Signed-off-by: Josua Mayer <josua@solid-run.com>
The Cubox has an unstable phy address - which can appear at either
address 0 (intended) or 4 (unintended).
SoM revision 1.9 has replaced the ar8035 phy with an adin1300, which
will always appear at address 1.
Change the reg property of the phy node to the magic value 0xffffffff,
which indicates to the generic phy driver that all addresses should be
probed. That allows the same node (which is pinned by phy-handle) to match
either the AR8035 PHY at both possible addresses, as well as the new one
at address 1.
Also add the new adi,phy-output-clock property for enabling the 125MHz
clock used by the fec ethernet controller, as submitted to Linux [1].
Linux solves this problem differently:
For the ar8035 phy it will probe both phy nodes in device-tree in order,
and use the one that succeeds. For the new adin1300 it expects U-Boot to
patch the status field in the DTB before booting
While at it also sync the reset-delay with the upstream Linux dtb.
[1] https://patchwork.kernel.org/project/netdevbpf/patch/20220428082848.12191-4-josua@solid-run.com/
Signed-off-by: Josua Mayer <josua@solid-run.com>
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as
well as providing the reference clock on CLK25_REF.
Add support for selecting the clock via device-tree properties.
This patch is based on the Linux implementation for this feature,
which has been added to netdev/net-next.git [1].
[2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/
Signed-off-by: Josua Mayer <josua@solid-run.com>
Currently, the adin driver fails to compile.
The original patch introducing the adin driver used the function
phy_get_interface_by_name to support the adi,phy-mode-override
property. Unfortunately, a few days before the adin patch
was accepted, another patch removed support for phy_get_interface_by_name:
123ca114e0
This patch refactors adin_get_phy_mode_override, implementing the logic in
the new function, ofnode_read_phy_mode, from the patch above.
Signed-off-by: Nate Drude <nate.d@variscite.com>
Tested-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
The imx8mn-ddr4-evk board has Ethernet support already, but the
lpddr4 board does not.
Add Ethernet support for the LPDDR4 variant too.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Add the new Apalis iMX8 product variant
0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT
the only difference to the product
0037 Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT
is the 8gb of RAM. Toradex strategy to choose the correct RAM timing in
SCFW is by fuses in the user area telling which RAM timing to load.
This commit makes use of this information to set the correct size of
the RAM and therefore distinguish between the new 0067 and 0037 product
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT
This module is identical to its 4GB counterpart
0037: Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT
except for the RAM size.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
The generated flash.bin does not boot the imx8mn evk LPDDR4 variant
as it misses the spl.bin description in binman.
Add its entry to fix the boot on the imx8mn evk LPDDR4 variant.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Arti Zirk <art@zirk.me>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
This test was written to match up with the list of compatibles in
drivers/i2c/tegra_i2c.c so adding another one requires the test to be
updated to match.
Fixes: 0d2105ae5e ("arm: tegra: Update some DT compatibles")
Signed-off-by: Tom Rini <trini@konsulko.com>
The pca9450 driver uses dm_i2c_{read,write}, which
are (unsurprisingly) only available with DM_I2C. Make sure one can't
create an unbuildable .config by adding proper dependencies.
While here, append "in SPL" to the prompt for the SPL_ variant so it
doesn't read the same as the one for the non-SPL_ variant.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
