Many boards/controllers/drivers don't support an I2C slave interface,
however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
default
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.
Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
__attribute__ follows gcc's documented syntax and is generally more
common than __attribute. This change is only asthetic and should not
affect functionality.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This additional text in the bootup log helps to see if the board is
configured for NAND-booting. Especially helpful for boards that can
boot from NOR and NAND (e.g. most of the AMCC eval boards).
Signed-off-by: Stefan Roese <sr@denx.de>
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.
Signed-off-by: Stefan Roese <sr@denx.de>
The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.
The cpus that get converted here:
at91rm9200
mpc512x
mpc5xxx
mpc8260
mpc8xx
ppc4xx
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: John Rigby <jrigby@freescale.com>
CC: Stefan Roese <sr@denx.de>
PCI outbound address map configuration doesn't match the
PCI memory address range covered by appropriate TLB entry
configuration for canyonlands causing machine check
exceptions while accessing PCI memory regions. This patch
provides a fix for this issue.
Kazuaki Ichinohe observed and reported this issue while
testing display output with PCI ATI video card on canyonlands.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.
Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.
On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".
This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.
The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.
The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration. The default will be the
"T2 Sample" value. A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".
Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent
between the two current users (lib_ppc/board.c, 44x SPD DDR2).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.
Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added support for a second memory bank to DDR autodetection for 440
platforms.
Made hardcoded values configurable.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.
Adjusted internal SRAM initialization to match updated user
manual recommendation.
OCM & ISRAM are now mapped as follows:
physical virtual size
ISRAM 0x4_0000_0000 0xE300_0000 256k
OCM 0x4_0004_0000 0xE304_0000 64k
A single TLB was used for this mapping.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().
Signed-off-by: Stefan Roese <sr@denx.de>
Also changed path in all linker scripts that reference this driver
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.
Any custom xilinx ppc405 board can be added very easily with no code
duplicity.
This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h
This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: Stefan Roese <sr@denx.de>
Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's. Default behavior
is the existing single CPU print output. Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.
Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
At a lot of places in the code the PIPE_INTERRUPT flags and friends
are used wrong. The wrong bits are compared to this flag resulting
in wrong conditions. Also there are macros that should be used for
PIPE_* flags.
This patch tries to fix them all, however, I was not able to test the
changes, because I do not have any of these boards.
Review required!
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].
The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus
Signed-off-by: Stefan Roese <sr@denx.de>
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).
Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B". DDR autocalibration Method_A scans the full range
of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B. Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.
The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1) SDRAM0_RQDC.[RQFD]
2) SDRAM0_RFDC.[RFFD]
This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:
1) SDRAM0_WRDTR.[WDTR]
2) SDRAM0_CLKTR.[CKTR]
3) SDRAM0_RQDC.[RQFD]
4) SDRAM0_RFDC.[RFFD]
and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This function is needed for the new NAND infrastructure. We only need
a dummy implementation though for the NDFC.
Signed-off-by: Stefan Roese <sr@denx.de>
