Commit graph

39 commits

Author SHA1 Message Date
Jim Liu
f49d616bea pinctrl: nuvoton: Add NPCM7xx pinctrl driver
Add Nuvoton BMC NPCM750 Pinmux and Pinconf support.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-10 13:37:32 -04:00
Tom Rini
4de720e98d Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05 08:33:32 -04:00
Samuel Holland
b799eabc7e sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:23:50 +01:00
Tom Rini
34d2b7f203 Prepare v2022.04-rc5
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Merge tag 'v2022.04-rc5' into next

Prepare v2022.04-rc5
2022-03-28 12:36:49 -04:00
Damien Le Moal
fd426b3106 k210: use the board vendor name rather than the marketing name
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15 17:43:11 +08:00
Ashok Reddy Soma
dbd673f14d pinctrl: zynqmp: Add pinctrl driver
Add pinctrl driver for Xilinx ZynqMP SOC. This driver is compatible with
linux device tree parameters for configuring pinmux and pinconf.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d7eefa83c8c0129f7243a25de56a289e948f6c6.1645626183.git.michal.simek@xilinx.com
2022-03-14 15:23:31 +01:00
Mark Kettenis
b814e0007e pinctrl: Add Apple pinctrl driver
This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17 17:04:58 -05:00
Sean Anderson
7224d5ccf8 pinctrl: Add support for Kendryte K210 FPIOA
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Heiko Schocher
5990b05951 powerpc, qe: add DTS support for parallel I/O ports
add DM support for parallel I/O ports on QUICC Engine Block

Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>

Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
  powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl

Commit-notes:
Open questions / discussion:

- I let the old none DM based implementation in code
  so boards should work with old implementation.

  This should be removed if all boards are converted to
  DM/DTS.

- Unfortunately linux DTS does not use "pinctrl-"
  properties, instead "pio-handle" properties.

  Even worser old U-Boot code initializes all pins
  defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
  table in board code. As linux does the same I decided
  to also scan through all subnodes containing "pio-map"
  property and initialize them too.

  The proper solution would be to check for "pio-handle"
  when a device is probed.

END
2020-09-17 06:09:53 +02:00
Stefan Bosch
8d393b2c22 pinctrl: add nexell driver
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
- doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt added.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Simon Glass
74749f1e84 x86: Add a generic Intel pinctrl driver
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Weijie Gao
3fad441c54 pinctrl: add support for MediaTek MT7628
This patch adds pinctrl support for mt7628, with a file for common pinmux
functions and a file for mt7628 which has additional support for pinconf.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Patrick Delaunay
8262435dd2 pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-12 16:09:13 +02:00
David Wu
e7ae4cf27a pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
Gregory CLEMENT
53bdae2418 pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Alexander Graf
caf2233b28 bcm283x: Add pinctrl driver
The bcm283x family of SoCs have a GPIO controller that also acts as
pinctrl controller.

This patch introduces a new pinctrl driver that can actually properly mux
devices into their device tree defined pin states and is now the primary
owner of the gpio device. The previous GPIO driver gets moved into a
subdevice of the pinctrl driver, bound to the same OF node.

That way whenever a device asks for pinctrl support, it gets it
automatically from the pinctrl driver and GPIO support is still available
in the normal command line phase.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-01-28 12:27:32 -05:00
Marek Vasut
910df4d07e pinctrl: rmobile: Add Renesas RCar pincontrol driver
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796
SoCs. This driver uses the PFC pin tables from Linux, thus letting us
share the occassional fixes to those tables. This driver also has a DT
support, so the pinmux is configured from DT instead of the ad-hoc setup
in board file.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-09-28 06:54:06 +09:00
Stefan Roese
8dd082a7e6 pinctrl: mvebu: Enable support for the Armada 37xx pinctrl driver
To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
2017-05-31 07:33:50 +02:00
maxims@google.com
4f0e44e466 aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:33 -04:00
Philipp Tomsich
51c7f34809 pinctrl: Kconfig: sort pinctrl config options to prevent future clutter
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:04 -04:00
Wenyou Yang
9319a756ff pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:50 -06:00
Felix Brack
44d5c371a6 Add single register pin controller driver
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack <fb@ltec.ch>
2017-03-26 13:23:42 -06:00
Vikas Manocha
94d5308412 PINCTRL: stm32f7: add pin control driver
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-17 14:15:14 -04:00
Patrice Chotard
0c56310252 STiH410: Add STi pinctrl driver
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-14 20:40:20 -04:00
Konstantin Porotchkin
656e6cc86b arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:04:52 +01:00
Beniamino Galvani
677b53580d pinctrl: add driver for meson-gxbb pin controller
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06 13:18:19 -04:00
Wenyou Yang
ac72e174f9 pinctrl: at91-pio4: Add pinctrl driver
AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-08-15 22:58:03 +02:00
Thomas Abraham
16ca80adc5 pinctrl: Add pinctrl driver support for Exynos7420 SoC
Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.

The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2016-05-25 10:00:18 +09:00
Wills Wang
a79d0643f4 drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x.
This is a simple pinctrl driver, it just support uart and spi pin-mux now.

Signed-off-by: Wills Wang <wills.wang@live.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Masahiro Yamada
1d22c4b1bd pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER
CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER
to guard the drivers/pinctrl/uniphier directory.

The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it
into CONFIG_PINCTRL_UNIPHIER.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:11:04 +09:00
Peng Fan
745df68d36 pinctrl: imx: Introduce pinctrl driver for i.MX6
Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
   To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
        pinctrl-names = "default";

        pinctrl_csi1: csi1grp {
                fsl,pins = <
                MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
                MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
                MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
                >;
        };

        [.....]
};
  there is no property named function or groups. So pinctrl_generic_set_state
  can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
   only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
   "
   set_state_simple op missing
   imx_pinctrl_set_state: i2c1grp
   mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
   write mux: offset 0x14c val 0x10
   select_input: offset 0x5d8 val 0x1
   write config: offset 0x3bc val 0x7f
   mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
   write mux: offset 0x148 val 0x10
   select_input: offset 0x5d4 val 0x1
   write config: offset 0x3b8 val 0x7f
   "
   this means imx6 pinctrl driver works as expected.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21 11:23:48 +01:00
Purna Chandra Mandal
5f266c60bf drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus
require no muxing.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:00 +01:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Masahiro Yamada
5dc626f836 pinctrl: uniphier: add UniPhier pinctrl core support
The core support for the pinctrl drivers for all the UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-23 23:21:32 +09:00
Simon Glass
bb4e4a5d96 rockchip: rk3288: Add pinctrl driver
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:24 -06:00
Masahiro Yamada
9c6a3c6772 pinctrl: sandbox: add sandbox pinctrl driver
This driver actually does nothing but test pinctrl uclass, and
demonstrate how things work.

To try this driver, uncomment /* #define DEBUG */ in the
drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
displayed.

  DRAM:  128 MiB
  sandbox pinmux: group = 1 (serial_a), function = 1 (serial)
  Using default environment

  In:    cros-ec-keyb
  Out:   lcd
  Err:   lcd
  Net:   Net Initialization Skipped
  eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000
  => i2c dev 0
  Setting bus to 0
  sandbox pinmux: group = 0 (i2c), function = 0 (i2c)
  sandbox pinconf: group = 0 (i2c), param = 3, arg = 1

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-31 07:57:29 -06:00
Masahiro Yamada
d90a5a30de pinctrl: add pin control uclass support
This creates a new framework for handling of pin control devices,
i.e. devices that control different aspects of package pins.

This uclass handles pinmuxing and pin configuration; pinmuxing
controls switching among silicon blocks that share certain physical
pins, pin configuration handles electronic properties such as pin-
biasing, load capacitance etc.

This framework can support the same device tree bindings, but if you
do not need full interface support, you can disable some features to
reduce memory foot print.  Typically around 1.5KB is necessary to
include full-featured uclass support on ARM board (CONFIG_PINCTRL +
CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX),
for example.

We are often limited on code size for SPL.  Besides, we still have
many boards that do not support device tree configuration.  The full
pinctrl, which requires OF_CONTROL, does not make sense for those
boards.  So, this framework also has a Do-It-Yourself (let's say
simple pinctrl) interface.  With CONFIG_PINCTRL_FULL disabled, the
uclass itself provides no systematic mechanism for identifying the
peripheral device, applying pinctrl settings, etc.  They must be
done in each low-level driver.  In return, you can save much memory
footprint and it might be useful especially for SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-31 07:57:29 -06:00