mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
rockchip: rk3288: Add pinctrl driver
Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
13d80ff5af
commit
bb4e4a5d96
4 changed files with 459 additions and 0 deletions
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@ -105,6 +105,15 @@ config SPL_PINCONF
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if PINCTRL || SPL_PINCTRL
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config ROCKCHIP_PINCTRL
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bool "Rockchip pin control driver"
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depends on DM
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help
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Support pin multiplexing control on Rockchip SoCs. The driver is
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controlled by a device tree node which contains both the GPIO
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definitions and pin control functions for each available multiplex
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function.
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config PINCTRL_SANDBOX
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bool "Sandbox pinctrl driver"
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depends on SANDBOX
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@ -1,4 +1,5 @@
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obj-y += pinctrl-uclass.o
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obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
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8
drivers/pinctrl/rockchip/Makefile
Normal file
8
drivers/pinctrl/rockchip/Makefile
Normal file
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@ -0,0 +1,8 @@
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#
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# Copyright (c) 2015 Google, Inc
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# Written by Simon Glass <sjg@chromium.org>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
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441
drivers/pinctrl/rockchip/pinctrl_rk3288.c
Normal file
441
drivers/pinctrl/rockchip/pinctrl_rk3288.c
Normal file
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@ -0,0 +1,441 @@
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/*
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* Pinctrl driver for Rockchip SoCs
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pmu_rk3288.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3288_pinctrl_priv {
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struct rk3288_grf *grf;
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struct rk3288_pmu *pmu;
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};
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static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
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{
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switch (pwm_id) {
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case PERIPH_ID_PWM0:
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rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
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GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
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break;
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case PERIPH_ID_PWM1:
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rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
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GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
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break;
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case PERIPH_ID_PWM2:
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rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
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break;
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case PERIPH_ID_PWM3:
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rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
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GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
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break;
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default:
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debug("pwm id = %d iomux error!\n", pwm_id);
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break;
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}
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}
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static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
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struct rk3288_pmu *pmu, int i2c_id)
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{
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switch (i2c_id) {
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case PERIPH_ID_I2C0:
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clrsetbits_le32(&pmu->gpio0b_iomux,
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GPIO0_B7_MASK << GPIO0_B7_SHIFT,
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GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
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clrsetbits_le32(&pmu->gpio0b_iomux,
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GPIO0_C0_MASK << GPIO0_C0_SHIFT,
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GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
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break;
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case PERIPH_ID_I2C1:
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rk_clrsetreg(&grf->gpio8a_iomux,
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GPIO8A4_MASK << GPIO8A4_SHIFT |
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GPIO8A5_MASK << GPIO8A5_SHIFT,
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GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
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GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
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break;
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case PERIPH_ID_I2C2:
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rk_clrsetreg(&grf->gpio6b_iomux,
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GPIO6B1_MASK << GPIO6B1_SHIFT |
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GPIO6B2_MASK << GPIO6B2_SHIFT,
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GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
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GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
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break;
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case PERIPH_ID_I2C3:
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rk_clrsetreg(&grf->gpio2c_iomux,
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GPIO2C1_MASK << GPIO2C1_SHIFT |
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GPIO2C0_MASK << GPIO2C0_SHIFT,
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GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
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GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
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break;
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case PERIPH_ID_I2C4:
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rk_clrsetreg(&grf->gpio7cl_iomux,
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GPIO7C1_MASK << GPIO7C1_SHIFT |
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GPIO7C2_MASK << GPIO7C2_SHIFT,
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GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
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GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
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break;
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case PERIPH_ID_I2C5:
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rk_clrsetreg(&grf->gpio7cl_iomux,
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GPIO7C3_MASK << GPIO7C3_SHIFT,
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GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
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rk_clrsetreg(&grf->gpio7ch_iomux,
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GPIO7C4_MASK << GPIO7C4_SHIFT,
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GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
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break;
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default:
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debug("i2c id = %d iomux error!\n", i2c_id);
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break;
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}
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}
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static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
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{
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switch (lcd_id) {
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case PERIPH_ID_LCDC0:
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rk_clrsetreg(&grf->gpio1d_iomux,
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GPIO1D3_MASK << GPIO1D0_SHIFT |
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GPIO1D2_MASK << GPIO1D2_SHIFT |
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GPIO1D1_MASK << GPIO1D1_SHIFT |
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GPIO1D0_MASK << GPIO1D0_SHIFT,
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GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
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GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
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GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
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GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
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break;
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default:
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debug("lcdc id = %d iomux error!\n", lcd_id);
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break;
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}
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}
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static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
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enum periph_id spi_id, int cs)
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{
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switch (spi_id) {
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case PERIPH_ID_SPI0:
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switch (cs) {
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case 0:
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rk_clrsetreg(&grf->gpio5b_iomux,
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GPIO5B5_MASK << GPIO5B5_SHIFT,
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GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
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break;
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case 1:
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rk_clrsetreg(&grf->gpio5c_iomux,
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GPIO5C0_MASK << GPIO5C0_SHIFT,
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GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
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break;
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default:
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goto err;
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}
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rk_clrsetreg(&grf->gpio5b_iomux,
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GPIO5B7_MASK << GPIO5B7_SHIFT |
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GPIO5B6_MASK << GPIO5B6_SHIFT |
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GPIO5B4_MASK << GPIO5B4_SHIFT,
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GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
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GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
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GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
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break;
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case PERIPH_ID_SPI1:
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if (cs != 0)
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goto err;
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rk_clrsetreg(&grf->gpio7b_iomux,
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GPIO7B6_MASK << GPIO7B6_SHIFT |
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GPIO7B7_MASK << GPIO7B7_SHIFT |
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GPIO7B5_MASK << GPIO7B5_SHIFT |
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GPIO7B4_MASK << GPIO7B4_SHIFT,
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GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
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GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
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GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
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GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
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break;
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case PERIPH_ID_SPI2:
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switch (cs) {
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case 0:
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rk_clrsetreg(&grf->gpio8a_iomux,
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GPIO8A7_MASK << GPIO8A7_SHIFT,
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GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
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break;
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case 1:
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rk_clrsetreg(&grf->gpio8a_iomux,
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GPIO8A3_MASK << GPIO8A3_SHIFT,
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GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
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break;
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default:
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goto err;
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}
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rk_clrsetreg(&grf->gpio8b_iomux,
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GPIO8B1_MASK << GPIO8B1_SHIFT |
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GPIO8B0_MASK << GPIO8B0_SHIFT,
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GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
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GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
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rk_clrsetreg(&grf->gpio8a_iomux,
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GPIO8A6_MASK << GPIO8A6_SHIFT,
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GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
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break;
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default:
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goto err;
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}
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return 0;
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err:
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debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
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return -ENOENT;
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}
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static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
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{
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switch (uart_id) {
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case PERIPH_ID_UART_BT:
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rk_clrsetreg(&grf->gpio4c_iomux,
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GPIO4C3_MASK << GPIO4C3_SHIFT |
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GPIO4C2_MASK << GPIO4C2_SHIFT |
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GPIO4C1_MASK << GPIO4C1_SHIFT |
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GPIO4C0_MASK << GPIO4C0_SHIFT,
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GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
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GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
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GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
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GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
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break;
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case PERIPH_ID_UART_BB:
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rk_clrsetreg(&grf->gpio5b_iomux,
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GPIO5B3_MASK << GPIO5B3_SHIFT |
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GPIO5B2_MASK << GPIO5B2_SHIFT |
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GPIO5B1_MASK << GPIO5B1_SHIFT |
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GPIO5B0_MASK << GPIO5B0_SHIFT,
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GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
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GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
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GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
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GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
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break;
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case PERIPH_ID_UART_DBG:
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rk_clrsetreg(&grf->gpio7ch_iomux,
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GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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break;
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case PERIPH_ID_UART_GPS:
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rk_clrsetreg(&grf->gpio7b_iomux,
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GPIO7B2_MASK << GPIO7B2_SHIFT |
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GPIO7B1_MASK << GPIO7B1_SHIFT |
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GPIO7B0_MASK << GPIO7B0_SHIFT,
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GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
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GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
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GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
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rk_clrsetreg(&grf->gpio7a_iomux,
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GPIO7A7_MASK << GPIO7A7_SHIFT,
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GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
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break;
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case PERIPH_ID_UART_EXP:
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rk_clrsetreg(&grf->gpio5b_iomux,
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GPIO5B5_MASK << GPIO5B5_SHIFT |
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GPIO5B4_MASK << GPIO5B4_SHIFT |
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GPIO5B6_MASK << GPIO5B6_SHIFT |
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GPIO5B7_MASK << GPIO5B7_SHIFT,
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GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
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GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
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GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
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GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
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break;
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default:
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debug("uart id = %d iomux error!\n", uart_id);
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break;
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}
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}
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static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
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{
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switch (mmc_id) {
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case PERIPH_ID_EMMC:
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rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
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GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
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GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
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GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
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GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
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GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
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GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
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GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
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GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
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rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
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GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
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rk_clrsetreg(&grf->gpio3c_iomux,
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GPIO3C0_MASK << GPIO3C0_SHIFT,
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GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
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break;
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case PERIPH_ID_SDCARD:
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rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
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GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
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GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
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GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
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GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
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GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
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GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
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GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
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/* use sdmmc0 io, disable JTAG function */
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rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
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break;
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default:
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debug("mmc id = %d iomux error!\n", mmc_id);
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break;
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}
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}
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static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
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{
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switch (hdmi_id) {
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case PERIPH_ID_HDMI:
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rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
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GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
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GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
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break;
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default:
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debug("hdmi id = %d iomux error!\n", hdmi_id);
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break;
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}
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}
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static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
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debug("%s: func=%x, flags=%x\n", __func__, func, flags);
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switch (func) {
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case PERIPH_ID_PWM0:
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case PERIPH_ID_PWM1:
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case PERIPH_ID_PWM2:
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case PERIPH_ID_PWM3:
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case PERIPH_ID_PWM4:
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pinctrl_rk3288_pwm_config(priv->grf, func);
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break;
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case PERIPH_ID_I2C0:
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case PERIPH_ID_I2C1:
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case PERIPH_ID_I2C2:
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case PERIPH_ID_I2C3:
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case PERIPH_ID_I2C4:
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case PERIPH_ID_I2C5:
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pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
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break;
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case PERIPH_ID_SPI0:
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case PERIPH_ID_SPI1:
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case PERIPH_ID_SPI2:
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pinctrl_rk3288_spi_config(priv->grf, func, flags);
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break;
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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case PERIPH_ID_UART4:
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pinctrl_rk3288_uart_config(priv->grf, func);
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break;
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case PERIPH_ID_LCDC0:
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case PERIPH_ID_LCDC1:
|
||||
pinctrl_rk3288_lcdc_config(priv->grf, func);
|
||||
break;
|
||||
case PERIPH_ID_SDMMC0:
|
||||
case PERIPH_ID_SDMMC1:
|
||||
pinctrl_rk3288_sdmmc_config(priv->grf, func);
|
||||
break;
|
||||
case PERIPH_ID_HDMI:
|
||||
pinctrl_rk3288_hdmi_config(priv->grf, func);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
|
||||
struct udevice *periph)
|
||||
{
|
||||
u32 cell[3];
|
||||
int ret;
|
||||
|
||||
ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
|
||||
"interrupts", cell, ARRAY_SIZE(cell));
|
||||
if (ret < 0)
|
||||
return -EINVAL;
|
||||
|
||||
switch (cell[1]) {
|
||||
case 44:
|
||||
return PERIPH_ID_SPI0;
|
||||
case 45:
|
||||
return PERIPH_ID_SPI1;
|
||||
case 46:
|
||||
return PERIPH_ID_SPI2;
|
||||
case 60:
|
||||
return PERIPH_ID_I2C0;
|
||||
case 62: /* Note strange order */
|
||||
return PERIPH_ID_I2C1;
|
||||
case 61:
|
||||
return PERIPH_ID_I2C2;
|
||||
case 63:
|
||||
return PERIPH_ID_I2C3;
|
||||
case 64:
|
||||
return PERIPH_ID_I2C4;
|
||||
case 65:
|
||||
return PERIPH_ID_I2C5;
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
|
||||
struct udevice *periph)
|
||||
{
|
||||
int func;
|
||||
|
||||
func = rk3288_pinctrl_get_periph_id(dev, periph);
|
||||
if (func < 0)
|
||||
return func;
|
||||
return rk3288_pinctrl_request(dev, func, 0);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops rk3288_pinctrl_ops = {
|
||||
.set_state_simple = rk3288_pinctrl_set_state_simple,
|
||||
.request = rk3288_pinctrl_request,
|
||||
.get_periph_id = rk3288_pinctrl_get_periph_id,
|
||||
};
|
||||
|
||||
static int rk3288_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
||||
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
|
||||
debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id rk3288_pinctrl_ids[] = {
|
||||
{ .compatible = "rockchip,rk3288-pinctrl" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_rk3288) = {
|
||||
.name = "pinctrl_rk3288",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = rk3288_pinctrl_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
|
||||
.ops = &rk3288_pinctrl_ops,
|
||||
.probe = rk3288_pinctrl_probe,
|
||||
};
|
||||
Loading…
Reference in a new issue