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Merge tag 'u-boot-atmel-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2021.04 cycle
This feature set includes the new board SAMA7G5 EK, the new evaluation
kit for Microchip AT91 SAMA7G5 SoC . The current board support includes
two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and
support for two Ethernet interfaces.
- Pinecube board support
- 64-bit FEL support
- mkimage support for eGON images (superseding mksunxiboot)
- Bluetooth BD address generation
- some fixes
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
ship with the controller default address.
Add a config option to fix it up so it can function properly.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Tested-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
[rebased]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Refactor setup_environment() so we can use the created sid for a
Bluetooth address too.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[rebased]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
It turns out that in rare cases, current analytical approach to detect
correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
with DDR3, incorrect DRAM configuration triggers write leveling error
which immediately stops initialization process. Exact reason why this
error appears isn't known. However, if correct configuration is used,
initalization works without problem.
In order to fix this issue, simply try another configuration when any
kind of error appears during initialization, not just those related to
rank and bus width.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Thomas Graichen <thomas.graichen@googlemail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For the sake of consistency (*) and order of initialization, i.e.
after we have got the ethernet address, interrupt and timer initialized,
try to initialize USB ethernet gadget.
*) for example, zynqmp uses same order.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
So far we did not support the BootROM based FEL USB debug mode on the
64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the
SPL runs in AArch64.
Returning back to AArch32 was not working as expected, since the RMR
reset into 32-bit mode always starts execution in the BootROM, but not
in the FEL routine.
After some debug and research and with help via IRC, the CPU hotplug
mechanism emerged as a solution: If a certain R_CPUCFG register contains
some magic, the BootROM will immediately branch to an address stored in
some other register. This works well for our purposes.
Enable the FEL feature by providing early AArch32 code to first save the
FEL state, *before* initially entering AArch64.
If we eventually determine that we should return to FEL, we reset back
into AArch32, and use the CPU hotplug mechanism to run some small
AArch32 code snippet that restores the initially saved FEL state.
That allows the normal AArch64 SPL build to be loaded via the sunxi-fel
tool, with it returning into FEL mode, so that other payloads can be
transferred via FEL as well.
Tested on A64, H5 and H6.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
The is_boot0_magic macro is missing parentheses around the macro
argument, breaking any usage with a more complex argument.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Switch the SPL boot image generation from using mksunxiboot to the new
sunxi_egon format of mkimage.
Verified to create identical results for all 152 Allwinner boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Samuel Holland <samuel@sholland.org>
So far we used the separate mksunxiboot tool for generating a bootable
image for Allwinner SPLs, probably just for historical reasons.
Use the mkimage framework to generate a so called eGON image the
Allwinner BROM expects.
The new image type is called "sunxi_egon", to differentiate it
from the (still to be implemented) secure boot TOC0 image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
To be able to easily share the Allwinner eGON BROM header structure
between the tools and the SPL code, move the struct definition into a
separate header file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
PineCube is an IP camera development kit released by Pine64.
It comes with the following compoents:
- A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC,
a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps
Ethernet port and FPC connectors for camera and daughter board.
- An OV5640-based camera module which is connected to the parallel CSI
bus of the mainboard.
- A daughterboard with several buttons, a SD slot, some IR LEDs, a
microphone and a speaker connector.
As the device tree is synchronized in a previous commit, just add it to
Makefile, create a new MAINTAINER item and provide a defconfig.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
On the XEA board (imx28) one needs in the SPL support for GPIO, MMC and
SPI. Two last ones are necessary for booting the device. The GPIO support
allows deciding which medium will be used. For example the GPIO DTS node
(gpio@0 at imx28.dtsi) has pinctrl parent (pinctrl@80018000) for which we
don't need driver asigned for correct operation.
In the spl/dts/dt-platdata.c the gpio@0 has index 4 and its parent -
pinctrl@80018000 has index 5.
In the bind_drivers_pass() function (at drivers/core/lists.c) call to
device_bind_by_name() for `fsl_imx23_pinctrl` returns -2, which is
expected.
With current setup - when the SPL_OF_PLATDATA_PARENT=y
The gpio@0 node with index 4 is skipped as its parent with 5 is not yet
bound. It cannot be as we don't need and provide the driver for it.
As a result the gpio@0 is never bound and we end up with bricked board in
the SPL stage.
When CONFIG_SPL_OF_PLATDATA_PARENT is NOT set, all entries from
spl/dts/dt-platdata.c are scanned in ascending index order, so gpio@0 is
properly initialized. For `fsl_imx_pinctrl` we simply check 10 times if
the driver for is available (which is not) and exit.
As a result the GPIOs are initialized and can be used in early SPL stage.
This commit fixes XEA regression introduced with e41651fffd.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The usage of the preboot feature is now controlled via a separate Kconfig
option - namely CONFIG_USE_PREBOOT.
It must be enabled for preboot code executing commands now defined in
CONFIG_PREBOOT (also moved to the Kconfig).
After defining both CONFIG_USE_PREBOOT and CONFIG_PREBOOT in
imx28_xea_defconfig the define of CONFIG_PREBOOT shall be removed from
xea.h as it is redundant.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
On the imx287 pin GPMI_WRN (GPIO0_25) no PullUP is available that can be
enabled.
To get the same behavior for both boot select pins (i.e. GPIO0_2{35})
disable pull UPs on both.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
TXC line is directly connected from the SoC to the KSZ9131 PHY. There
is a transient state on this signal, before configuring it to RGMII,
which leads to packet transmit being blocked.
Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes
the issue.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Obtain two MAC addresses from the two EEPROMs and configure the two
available Ethernet interfaces accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add node for flx1 i2c1 subnode (and alias to bus 0)
This bus has two eeprom devices connected.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add new config for storing environment from sdmmc0.
Also clean-up sama7g5ek_emmc1 to point to the proper mmc device.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Clean-up boot command to use the predefined device and part for FAT
environment.
According to this device and partition, select the proper boot media.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Enable sdmmc0 on this board. A non-removable eMMC is connected on this
block.
Configure pincontrol accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
SDMMC1 requires clock specification with assigned-clocks, such that
the PMC will know which parent to assign and the initial start-up frequency.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Get rid of software defined MCK and switch to PMC bindings
for IPs currently present in device tree.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
