Commit graph

89659 commits

Author SHA1 Message Date
Guochun Huang
39fb8acac4 clk: rk3588: Add 742.5M parameter for PLL
For a specific frequency.

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
Elaine Zhang
bdb35a2863 clk: rockchip: rk3568: support dclk_vop select more parent clks
For dclk_vop to support more frequencies.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
Jonas Karlman
de7f4bb1f1 rockchip: rk3568-radxa-e25: Enable pcie3x1 node
Enable mini PCIe slot, pcie3x1 node, now that the PCIe PHY driver
support bifurcation.

A pinctrl is assigned for reset-gpios or the device may freeze running
pci enum and nothing is connected to the mini PCIe slot.

Also drop the AHCI_PCI Kconfig option as this option is not required for
a functional M.2 SATA drive slot.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-10-23 18:21:55 +08:00
Andre Przywara
fa066df62e sunxi: add MangoPi MQ-R board support
The MangoPi MQ-R board uses an Allwinner T113s Soc (with 128MB of
embedded DRAM), support for which was just added to the code.

Since the devicetree was already synced from the latest Linux kernel
tree, all we need is a _defconfig file to add support for the board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-23 01:00:56 +01:00
Sam Edwards
352ba256da sunxi: psci: implement PSCI on R528
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Kevin Amadiva <kevin.amadiva@mec.at>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
b1fbc20e76 sunxi: psci: stop modeling register layout with C structs
Since the sunxi support nowadays generally prefers #defined register
offsets instead of modeling register layouts using C structs, now is a
good time to do this for PSCI as well. This patch moves away from using
the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c.

The former struct and its associated header file existed only to support
PSCI code, so also delete them altogether.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
3f31c6f103 sunxi: psci: refactor register access to separate functions
This is to prepare for R528, which does not have the typical
"CPUCFG" block; it has a "CPUX" block which provides these
same functions but is organized differently.

Moving the hardware-access bits to their own functions separates the
logic from the hardware so we can reuse the same logic.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Sam Edwards
f9670d7b0b sunxi: psci: clean away preprocessor macros
This patch restructures psci.c to get away from the "many different
function definitions switched by #ifdef" paradigm to the preferred style
of having a single function definition with `if (IS_ENABLED(...))` to
make the optimizer include only the appropriate function bodies instead.

There are no functional changes here.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
beeace9ba1 sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.

Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.

This disentangles the architecture specific header files from the
generic code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Okhunjon Sobirjonov
5b7c58fbba sunxi: R528: add SMHC2 pin pull ups support
Add support for eMMC (SMHC2) pin pull ups for R528 boards.

The D1 and T113s (and even R329) SoCs do not support 8-bit eMMC anymore,
so it's just four data pins to cover here.

Signed-off-by: Okhunjon Sobirjonov <Okhunjon.Sobirjonov@Mec-electronics.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: adjust commit message]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
95168d77d3 sunxi: add Allwinner R528/T113 SoC support
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).

This adds the new Kconfig stanza, using the two newly introduced symbols
for the new SoC generation and pincontroller. It also adds the new symbols
to the relavent code places, to set all the hardcoded bits directly.

We need one DT override:
The ARM core version of the DT specifies the CPUX watchdog as
"reserved", which means it won't be recognised by U-Boot. Override this
in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
so that the generic reset driver will work.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
124289bd56 sunxi: add R528/T113-s3/D1(s) DRAM initialisation code
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and cleaned up, to match previous
DRAM routines for other SoCs, and also to be closer to U-Boot's coding
style and support routines.
The actual DRAM chip timing parameters are included in the main file,
since they cover all DRAM types, and are protected by a new Kconfig
CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only
the relevant settings, at build time.

The relevant DRAM chips/board specific configuration parameters are
delivered via Kconfig, so this code here should work for all supported
SoCs and DRAM chips combinations.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-10-22 23:41:52 +01:00
Andre Przywara
8bddb9742b Kconfig: sunxi: prepare for using drivers/ram/sunxi
At the moment all Allwinner DRAM initialisation routines are stored in
arch/arm/mach-sunxi, even though those "drivers" are just a giant
collection of writel's, without any architectural dependency.

The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V
cores) share the same die, so should share the same DRAM init routines as
well.

To prepare for this, add a new sunxi directory inside drivers/ram, and
add some stub entries to prepare for the addition of the share DRAM code
for those SoCs.

The RISC-V D1(s) SoCs will probably use SPL_DM, so for that SoC this
would be the right directory anyway.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
a94c9c809b sunxi: clock: support D1/R528 PLL6 clock
The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.

Add code to support this version of "PLL6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
39ba474698 sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Samuel Holland
b9a91b98e8 clk: sunxi: Add support for the D1 CCU
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
ad9dcb5001 pinctrl: sunxi: add Allwinner D1 pinctrl description
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:41:51 +01:00
Andre Przywara
4a9e89a3e3 sunxi: introduce NCAT2 generation model
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the clock controller significantly. We added a
CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits.

Now the Allwinner D1 changes the memory map again, and also extends the
pincontroller, among other peripherals.
To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol,
this name is reportedly used in the Allwinner BSP code, and prevents us
from inventing our own name.

Add this new symbol to some guards that were already checking for the H6
generation, since many features are shared between the two (like the
renovated clock controller).

This paves the way to introduce a first user of this generation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:41:46 +01:00
Andre Przywara
452369cd0c pinctrl: sunxi: add new D1 pinctrl support
For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy interfaces.

Add a new Kconfig symbol to differenciate between the two generations of
pincontrollers, and just use that to just switch some basic symbols.
The rest is already abstracted enough, so works out of the box.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
1da48c99de pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h
On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed anymore.

To avoid a dependency on CPU specific headers in an arch specific
directory, move the definition of the pinctroller MMIO base address into
the sunxi_gpio.h header, because the SPL routines for GPIO should be the
only one needing this address.
This is a first step towards getting rid of cpu_sun[x]i.h completely,
and allows to remove the inclusion of that file from the sunxi_gpio.h
header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-10-22 23:40:57 +01:00
Andre Przywara
207ed0a3dd pinctrl: sunxi: remove GPIO_EXTRA_HEADER
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the SPL,
but this should become the exception, not the rule.

Make this more obvious by removing the definition of GPIO_EXTRA_HEADER,
and just force every legacy user of platform specific GPIO to include
the new sunxi_gpio.h header explicitly. Everyone doing so should feel
ashamed and should find a way to avoid it from now on.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
30097ee3d2 pinctrl: sunxi: remove struct sunxi_gpio
So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to drop "struct sunxi_gpio", that described that
MMIO frame in a C struct. That approach is somewhat frowned upon in the
Linux world and rarely used there, though still popular with U-Boot.

Switching from a C struct to a "base address plus offset" approach allows
to switch between the two models more dynamically, without reverting to
preprocessor macros and #ifdef's.

Model the pinctrl MMIO register frame in the usual "base address +
offset" way, and replace a hard-to-parse CPP macro with a more readable
static function.
All the users get converted over. There are no functional changes at
this point, it just prepares the stages for the D1 and friends.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:57 +01:00
Andre Przywara
316ec7ffbd pinctrl: sunxi: add GPIO in/out wrappers
So far we were open-coding the pincontroller's GPIO output/input access
in each function using that.

Provide functions that wrap that nicely, and follow the existing pattern
(set/get_{bank,}), so users don't need to know about the internals, and
we can abstract the new D1 pinctrl more easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:56 +01:00
Andre Przywara
20b78c55e7 pinctrl: sunxi: move pinctrl code
Move the existing sunxi-specific low level pinctrl routines from
arch/arm/mach-sunxi into the existing GPIO code under drivers/gpio, so
that the common code can be shared outside of arch/arm.

This also takes the opportunity to move some definitions from our
header file into the driver C file, as they are private to the driver
and are not needed elsewhere.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:56 +01:00
Andre Przywara
5ad98c57b8 sunxi: remove CONFIG_MACPWR
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and use a DM driver there, we should use the DT
instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
that regulator and enable it, at probe time. Then drop the current code
from board.c, which was doing that job before.
This allows us to remove the MACPWR Kconfig definition and the respective
values from the defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
2023-10-22 23:40:56 +01:00
Andre Przywara
091442993c net: sunxi_emac: chase DT nodes to find PHY regulator
At the moment the sun4i EMAC driver relies on hardcoded CONFIG_MACPWR
Kconfig symbols to enable potential PHY regulators. As we want to get rid
of those, we need to find the regulator by chasing up the DT.

The sun4i-emac binding puts the PHY regulator into the MDIO node, which
is the parent of the PHY device. U-Boot does not have (and does not
need) an MDIO driver, so we need to chase down the regulator through the
EMAC node: we follow the "phy-handle" property to find the PHY node,
then go up to its parent, where we find the "phy-supply" link to the
regulator. Let U-Boot find the associated regulator device, and put that
into the private device struct, so we can find and enable the regulator
at probe time, later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:56 +01:00
Andre Przywara
ae79c1d01f sunxi: remove CONFIG_SATAPWR
The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
enables the power for a SATA harddisk.
In the DT this is described with the target-supply property in the AHCI
DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
only in U-Boot proper, and use a DM driver for AHCI there, we should use
the DT instead of hardcoding this.

Add code to the sunxi AHCI driver to check the DT for that regulator and
enable it, at probe time. Then drop the current code from board.c, which
was doing that job before.
This allows us to remove the SATAPWR Kconfig definition and the
respective values from the defconfigs.
We also select the generic fixed regulator driver, which handles those
GPIO controlled regulators.

Please note that the OrangePi Plus is a bit special here, it's a H3
board without native SATA, but with a USB-to-SATA bridge. The DT models
the SATA power via a VBUS supply regulator, which we don't parse yet in
the USB PHY driver. Use the hardcoded CONFIG_USB3_VBUS_PIN for that
board meanwhile.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-22 23:40:47 +01:00
Svyatoslav Ryhel
846dcae733 video: tegra20: dsi: use regulator_set_enable_if_allowed
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators and may be further expanded on all
regulators.

Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-10-22 19:28:31 +02:00
Svyatoslav Ryhel
66ac14f7ef video: simple_panel: use regulator_set_enable_if_allowed
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators and may be further expanded on all
regulators.

Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-10-22 19:25:10 +02:00
Svyatoslav Ryhel
251ff34932 video: pwm_backlight: use regulator_set_enable_if_allowed
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators and may be further expanded on all
regulators.

Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-10-22 19:23:47 +02:00
Andre Przywara
a14c250625 sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6
This copies in some devicetree files from the official Linux kernel tree,
v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares
many devices with its RISC-V sibling, the Allwinner D1(s). This is the
reason for the core .dtsi files landing in the arch/riscv directory.

We are only adjusting the include path to accommodate for the differences
in the U-Boot build system.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-22 01:12:26 +01:00
Andre Przywara
1fe28c0aa6 sunxi: dts: arm: update devicetree files from Linux-v6.6-rc6
Sync the devicetree files from the official Linux kernel tree, v6.6-rc6.
This is covering Allwinner SoCs with 32-bit ARM cores, minus the T113s
board and related .dtsi files, which come separately.

Only small changes: Bluetooth got enabled on the C.H.I.P., and a clock
got renamed. More interesting is the addition of a board, for which
U-Boot enablement patches are pending.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-22 01:12:26 +01:00
Andre Przywara
95c3b0635e sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6
Sync the devicetree files from the official Linux kernel tree, v6.6-rc6.
This is covering Allwinner SoCs with 64-bit ARM cores.

Only small cosmetic changes (clock name fixed), but we add the DT for
the new OrangePi Zero 3 board, for which U-Boot enablement patches are
pending.

As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-22 01:12:25 +01:00
Tom Rini
9a3a58396b Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- kirkwood: Pogo v4: Enable LTO (Tony)
2023-10-20 12:54:33 -04:00
Tony Dinh
1060db76b0 arm: kirkwood: Pogo v4: Enable LTO
Enable building Pogo V4 u-boot image with LTO, which results in about 30K
reduction in size.

Rebased to latest master and resend.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-10-20 11:57:26 +02:00
Tom Rini
a65c3990e5 Merge branch 'master_uart_test' of https://source.denx.de/u-boot/custodians/u-boot-sh 2023-10-19 16:27:09 -04:00
Paul Barker
966caedfa8 serial: sh: Add RZ/G2L SCIF support
Extend the existing driver to support the SCIF serial ports on the
Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that if
there is a reset signal defined in the device tree, it is de-asserted
before we try to talk to the SCIF module.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
2023-10-19 17:03:20 +02:00
Paul Barker
0f924d88fa serial: sh: Fix error handling
The current SCIF error handling is broken for the RZ/G2L. After a break
condition has been triggered, the current code is unable to clear the
error and serial port output never resumes.

The RZ/G2L datasheet says that most error conditions are cleared by
resetting the relevant error bits in the FSR & LSR registers to zero.
To clear framing errors on SCIF ports, the invalid data also needs to be
read out of the receive FIFO.

After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3
and even SH7751 SoCs, it's clear that this is the way to clear errors
for all of these SoCs.

While we're here, annotate the handle_error() function with a couple of
comments as the reads and writes themselves don't immediately make it
clear what we're doing.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tested-by: Chris Paterson <chris.paterson2@renesas.com> # HiHope RZ/G2M board
Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
2023-10-19 17:03:15 +02:00
Tom Rini
e463222cce Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
+ riscv: Add Zbb support
+ riscv: Add preliminary RISC-V falcon mode support
+ riscv: Remove dram_init_banksize()
+ andes: rearrange PLICSW scheme
+ visionfive2: enable bootstage configs
2023-10-19 09:40:04 -04:00
Tom Rini
48bc9de282 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
- sandbox: watchdog: Avoid an error on startup (Simon)
- nuvoton: Fix reset/expire function error (Jim)
2023-10-19 09:39:00 -04:00
Yu Chien Peter Lin
bc5a50452b riscv: Add Zbb support for building U-Boot
This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19 17:29:50 +08:00
Randolph
03a4504659 riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.

Moving the DTB in front of the kernel can avoid this error.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19 17:29:33 +08:00
Randolph
fe192679ef andes: config: add riscv falcon mode for ae350 platform
Fork from ae350_rv[32/64]_spl_[xip]_defconfig and
append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19 17:29:33 +08:00
Randolph
58fa2a5aa1 spl: riscv: add os type for next booting stage
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:33 +08:00
Randolph
9421e41981 Makefile: delete file *.itb when make clean
Delete the output file *.itb

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:33 +08:00
Randolph
d311df8b31 riscv: dts: binman: add condition for opensbi os boot
Add condition for OpenSBI OS boot mode, by default it is not enabled.
By default, binman creates the output file u-boot.itb.
If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created
after compilation instead of the default u-boot.itb.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:33 +08:00
Randolph
e09a2287c1 riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
Introduce common Kconfig symbol for riscv architecture.
This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM,
the Falcon boot is a shortcut boot method for SD/eMMC targets. It
skips the loading the RAM version U-Boot. Instead, it will loads
the FIT image and boots directly to Linux.

When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after
compilation instead of the default u-boot.itb. It initialises memory
with the U-Boot SPL at the first stage, just as a normal boot process
does at the beginning. Instead of jumping to the U-Boot proper from
OpenSBI before booting the Linux kernel, the RISC-V falcon mode
process jumps directly to the Linux kernel to gain shorter booting time.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:33 +08:00
Randolph
5367b9e798 spl: riscv: opensbi: change the default os_type as varible
In order to introduce the Opensbi OS boot mode, the next stage boot
image of OpenSBI should be configurable.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:33 +08:00
Randolph
04b2123b4d riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy
Source hart information is not necessary in IPI, so we could
use single-bit-per-hart strategy to rearrange PLICSW mapping.

Bit 0 of Interrupt Pending Bits is hardwired to 0.
Therefore, we use bit 1 to send IPI to hart 0,
bit 2 to hart 1, ..., and so on.

Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19 17:29:33 +08:00
Mayuresh Chitale
5a348ccf02 riscv: binman: Fix compilation error
Some platforms may not have any DDR memory below 4G and for such platforms
the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to
which the u-boot build fails with below error:

u-boot/arch/riscv/dts/binman.dtsi:30.14-25
Value out of range for 32-bit array element
u-boot/arch/riscv/dts/binman.dtsi:43.14-25
Value out of range for 32-bit array element
u-boot/arch/riscv/dts/binman.dtsi:44.15-26
Value out of range for 32-bit array element
FATAL ERROR: Syntax error parsing input tree

Fix by setting the address-cells property to 2 and converting load
addresses to 64 bit values.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19 17:29:32 +08:00