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pinctrl: sunxi: add Allwinner D1 pinctrl description
Apart from using the new pinctrl MMIO register layout, the Allwinner D1 and related SoCs still need to usual set of mux values hardcoded in U-Boot's pinctrl driver. Add the values we need so far to this list, so that DM based drivers will just work without further ado. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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2 changed files with 36 additions and 0 deletions
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@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R
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default MACH_SUN50I_H616
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select PINCTRL_SUNXI
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config PINCTRL_SUN20I_D1
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bool "Support for the Allwinner D1/R528 PIO"
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select PINCTRL_SUNXI
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endif
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@ -598,6 +598,32 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
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.num_banks = 3,
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};
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static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
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{ "emac", 8 }, /* PE0-PE15 */
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{ "gpio_in", 0 },
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{ "gpio_out", 1 },
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{ "i2c0", 4 }, /* PB10-PB11 */
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{ "mmc0", 2 }, /* PF0-PF5 */
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{ "mmc1", 2 }, /* PG0-PG5 */
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{ "mmc2", 3 }, /* PC2-PC7 */
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{ "spi0", 2 }, /* PC2-PC7 */
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#if IS_ENABLED(CONFIG_UART0_PORT_F)
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{ "uart0", 3 }, /* PF2,PF4 */
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#else
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{ "uart0", 6 }, /* PB0-PB1, PB8-PB9, PE2-PE3 */
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#endif
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{ "uart1", 2 }, /* PG6-PG7 */
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{ "uart2", 7 }, /* PB0-PB1 */
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{ "uart3", 7 }, /* PB6-PB7 */
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};
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static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
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.functions = sun20i_d1_pinctrl_functions,
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.num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions),
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.first_bank = SUNXI_GPIO_A,
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.num_banks = 7,
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};
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static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
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{ "emac", 4 }, /* PD8-PD23 */
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{ "gpio_in", 0 },
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@ -863,6 +889,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
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.data = (ulong)&sun9i_a80_r_pinctrl_desc,
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},
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#endif
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#ifdef CONFIG_PINCTRL_SUN20I_D1
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{
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.compatible = "allwinner,sun20i-d1-pinctrl",
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.data = (ulong)&sun20i_d1_pinctrl_desc,
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},
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#endif
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#ifdef CONFIG_PINCTRL_SUN50I_A64
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{
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.compatible = "allwinner,sun50i-a64-pinctrl",
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