Commit graph

25 commits

Author SHA1 Message Date
Lokesh Vutla
642cdc13f6 ARM: OMAP5+: Remove unnecessary EFUSE settings
Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.

Reported-by: Griffis, Brad <bgriffis@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-12-04 08:12:38 -05:00
SRICHARAN R
6c70935d75 ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-12-04 08:12:08 -05:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Axel Lin
87bd05d78f ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.

This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.

Thanks for Lubomir Popov to provide valuable comments to fix this issue.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-07-02 09:21:16 -04:00
Sricharan R
92b0482c17 ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
e9d6cd042d ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
af1d002f89 ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
SRICHARAN R
f92f2277a6 ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
Lokesh Vutla
0b1b60c779 ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.

There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.

In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'

In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-05-10 08:25:55 -04:00
Lokesh Vutla
de62688bb6 arm: dra7xx: Add silicon id support for DRA752 soc
Adding CPU detection support for the DRA752 ES1.0 soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:39:57 -04:00
Lokesh Vutla
d4e4129c31 arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4d986ee27 ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
SRICHARAN R
eed7c0f727 ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
ef1697e99f ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
c43c8339fe ARM: OMAP4+: Make control module register structure generic
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
9ca8bfea80 ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
Lokesh Vutla
784ab7c545 OMAP5: EMIF: Add support for DDR3 device
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
Lokesh Vutla
eb4e18e89e OMAP5: Configure the io settings for omap5432 uevm board
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
Lokesh Vutla
0a0bf7b217 OMAP5: ADD chip detection for OMAP5432 SOC
This patch adds chip detection for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:23 +02:00
SRICHARAN R
0696473be7 OMAP5: reset: Use cold reset in case of 5430ES1.0
Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:25 +02:00
SRICHARAN R
002a2c0c66 OMAP4/5: Make the sysctrl structure common
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
087189fb54 OMAP4/5: Make the silicon revision variable common.
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
cdd50a8d07 OMAP5: hwinit: Add the missing break statement
The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:24 +02:00
SRICHARAN R
6ad8d67de8 OMAP5: io: Configure the io settings for omap5430 sevm board.
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
Sricharan
508a58fa8e omap5: Add minimal support for omap5430.
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00