In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).
This situation turns out to lead to a run time freeze with certain
toolchains.
Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73 ("nand: sunxi: Fix modulo
by zero error").
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.
For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.
Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
A previous commit introduced the use of binman in the SPL.
After the binman_sym call over the 'pos' symbol, the output value is
checked against BINMAN_SYM_MISSING (-1UL). According to the
documentation (tools/binman/README), when it comes to the 'pos'
attribute:
pos:
This sets the position of an entry within the image. The first
byte of the image is normally at position 0. If 'pos' is not
provided, binman sets it to the end of the previous region, or
the start of the image's entry area (normally 0) if there is no
previous region.
So instead of checking if the return value is BINMAN_SYM_MISSING, we
should also check if the value is not null.
The failure happens when using both the SPL file and the U-Boot file
independently instead of the concatenated file (SPL + padding + U-Boot).
This is because the U-Boot binary file alone does not have the U-Boot
header while it is present in the concatenation file. Not having the
header forces the SPL to discover where it should load U-Boot. The
binman_sym call is supposed to do that but fails. Because of the wrong
check, the destination address was set to 0 while it should have been
somewhere in RAM. This, obviously, stalls the board.
Fixes: 8bee2d251a ("binman: Add binman symbol support to SPL")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
HSDK board has sst26wf016 SPI flash IC which we want to support.
Add SPI controller, CS-gpio and SPI flash nodes to hsdk device tree.
Enable corresponding options in hsdk defconfig.
For SPI write functionality to work we need [1] which
adds support of sst26xxx ICs.
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=35796
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This patch add support of hsdk platform-specific commands:
hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq
environment variables/command line arguments
hsdk_clock get - save clock frequencies to axi_freq, cpu_freq
and tun_freq environment variables
hsdk_clock print - show CPU, AXI, DDR and TUNNEL current
clock frequencies.
hsdk_clock print_all - show all currently used clock frequencies.
hsdk_init - setup board HW in one of pre-defined configuration
(hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 /
hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4)
hsdk_go - run baremetal application on hsdk configured
by hsdk_init command.
This patch changes default behaviour of 'bootm' command:
now we are able to set number of CPUs to be kicked by setting
'core_mask' environment variable before 'bootm' command run.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Some device tree nodes (like ethernet, ohci, ehci) in axs10x_mb.dtsi
were copied from linux device tree, so they have interrupts properties.
As we don't use interrupts in uboot we don't have interrupt controller
node in AXS10x device tree. In result we get warnings when we compile
such device tree.
So remove unused interrupts properties to get rid of this warnings.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This header needs to know 'fdt_region' is a struct for the
fit_region_make_list() prototype.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
fdt_region.c does not depend on anything in libfdt_internal.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This macro is locally referenced in common/image-fdt.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.
It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):
* Note: We consider that crossing any level with #size-cells == 0 to mean
* that translation is impossible (that is we are not dealing with a value
* that can be mapped to a cpu physical address). This is not really specified
* that way, but this is traditionally the way IBM at least do things
To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Reported-by: Martin Fuzzey <mfuzzey@parkeon.com>
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass <sjg@chromium.org>
dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The cast breaks the pointer on 64bit archs, so lets get rid of it.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Use live dt interface for pinctrl_select_state_full()
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add api for who can not get phandle from a device property.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch enabled PCIe port on both devel-board
and espressobin board.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu <xigu@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch added a new region of 32MiB AT 0xe800.0000
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Victor Gu <xigu@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the new pinctrl/gpio driver is used, so this patch removes
the old board specific pin control settings.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has
added new pinctrl nodes.
This reverts commit f7cab0f95b.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch corrects below mpp definitions for armada 3720 DB board
and ESPRESSOBin board:
- "smi" pins group is added and "smi" function is set for eth0;
- Now pcie pins are used as gpio to implement PCIe function in
hardware, so "pcie" group function is changed to "gpio".
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch corrects below mpp definitions:
- The sdio_sb group is composed of 6 pins and not 5;
- The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
- Pin of group "pmic0" is mpp1[6] but not mpp1[16];
- Pin of group "pmic1" is mpp1[7] but not mpp1[17];
- A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
bitmask is bit4;
- Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
bit5 | bit9 | bit10 but not bit4;
- Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
bit11 | bit12 | bit13.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.
Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.
The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43284
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43286
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).
Reviewed-on: http://vgitil04.il.marvell.com:8080/43285
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add mmc pins, pcie pins and sdio pins definition and do these pins'
configuration for DB board and espressobin board;
Add uart2 pins configuration for DB board.
Reviewed-on: http://vgitil04.il.marvell.com:8080/40914
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enable the PINCTRL and GPIO support, including the GPIO
command on the Armada 3720 espressobin board.
Reviewed-on: http://vgitil04.il.marvell.com:8080/40746
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The various load address values are taken from the a37xx configuration
and match the dowstream 'u-boot-2017.03-armada-17.10' release where
appropriate.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This makes the network devices usable when booting a blank board over
UART, with no pre-configured MAC address stored in the environment area.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.
This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.
Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.
With this commit, Intel Galileo board boots again.
Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The get_codeseg32() wants to know if a passed in descriptor has
flag GDT_NOTSYS set (desc & GDT_NOTSYS), not whether desc and
GDT_NOTSYS are not != 0 (desk && GDT_NOTSYS).
This is an obvious typo. Fix it up.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.
There are two methods to delivery dtb.
1 Pass from loader:
When u-boot boot from RAM, gdb or loader can pass dtb
via a2 to u-boot dynamically. Of course gdb or loader
shall be in charge of dtb delivery.
2 Configure CONFIG_SYS_FDT_BASE:
It can be configured as RAM or ROM base statically,
no mater u-boot boot from RAM or ROM.
If it was configured as ROM base, dtb can be burned
into ROM(spi flash) by spi driver.
Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Remove CONFIG_MMC_NDS32 from the three config
(adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig).
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
