My Bootlin address is the preferred one now.
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20221203214939.56608-1-luca@lucaceresoli.net
Signed-off-by: Michal Simek <michal.simek@amd.com>
vck190 system controller low level setup is the same for revB that's why
also create symlink to revA.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221017094818.17996-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Before this patch you could see in the log:
U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:29:27 +0200)
PMUFW: v1.1
Loading new PMUFW cfg obj (32 bytes)
PMUFW: No permission to change config object
Loading new PMUFW cfg obj (2032 bytes)
where it is visible that permission is check before sending PMUFW
configuration (big size).
When this patch is applied it is visible that order is correct.
U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:47:08 +0200)
Loading new PMUFW cfg obj (2032 bytes)
PMUFW: v1.1
Loading new PMUFW cfg obj (32 bytes)
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0bf4f46d670023da4f848790eece6fff22090c2.1664962765.git.michal.simek@amd.com
Compiling with GCC-12 leads to an error:
+board/xilinx/common/board.c:479:37: error: the comparison will always
evaluate as 'true' for the address of 'mac_addr' will never be NULL
[-Werror=address]
+ 479 | if (!desc->mac_addr[i])
+ | ^
Remove the redundant check.
Fixes: a03b594738 ("xilinx: board: Add support for additional card detection")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Link: https://lore.kernel.org/r/20221008091317.52838-1-heinrich.schuchardt@canonical.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In function ‘set_dfu_alt_info’ a comparison of a u8 value against
0 is done. Since it is always false, change the signature of this
function to use an `int` instead, which match the type used in caller:
`multi_boot()`.
Fix the following warning triggered with W=1:
board/xilinx/zynqmp/zynqmp.c:651:23:
warning: comparison is always false due to limited range of data type
[-Wtype-limits]
651 | if (multiboot < 0)
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004055254.26246-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
cpu-info.c defines print_cpuinfo(), but neglected to
include its declaration, causing the following sparse and
compile time warnings:
board/xilinx/common/cpu-info.c:10:5:
warning: no previous prototype for 'print_cpuinfo'
[-Wmissing-prototypes]
Include init.h, which includes the missing declaration.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221004055053.26047-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYzGwogAKCRDKSWXLKUoM
Ial4AJ9+4WHn0MV2X7gK1fyh4lUW7ggPhQCggsYlSoACgMgdji17SAPhCv/W3IA=
=BmA9
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar to Versal but it will
likely diverge in longer run.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
Commit 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
changed type of ram_top member from ulong to phys_addr_t but did not
changed types in board_get_usable_ram_top() function which returns value
for ram_top.
So change ulong to phys_addr_t type also in board_get_usable_ram_top()
signature and implementations.
Fixes: 37dc958947 ("global_data.h: Change ram_top type to phys_addr_t")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Code supports board detection based on information available in EEPROM in
legacy or FRU format. But this is not enough for emulation and simulation
systems which are lacking these identification EEPROMs. But SOC itself has
normally registers for SOC identification. Based on them it is possible to
compose detected name. That's why prepare infrastructure in common location
for SOC platform detection which is called before board platform detection.
SOC platform detection shouldn't detect real silicon and should fallback to
current existing mechanism to identify boards based on EEPROMs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
The commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.
On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=30000000 size=10000000
flags=4)" which is shown when bdinfo is called.
Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
The commit 53b406369e ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
The user provided key address was not flushed in struct aes because of
the flushing location in the function.
Signed-off-by: Janne Ylalehto <ylalehto@gmail.com>
Link: https://lore.kernel.org/r/20220816124525.19671-1-ylalehto@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
UUID is already recorded when FRU is parsed but it is not copied to local
structures and exported to variable that's why simply add it.
Data is saved in binary format but there must be conversion to string for
exporting it to variable and string should be in uuid format too.
One way how to use it directly is to setup pxeuuid based on it. For
example via preboot with "setenv pxeuuid ${board_uuid}"
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1dfa4b4220a508abc05351da2119880811b77612.1658413156.git.michal.simek@amd.com
With commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.
Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
The set_dfu_alt_info function use the CONFIG_SYS_SPI_U_BOOT_OFFS define
to set the dfu_alt_info environment variable for qspi boot mode. Guard
the usage of CONFIG_SYS_SPI_U_BOOT_OFFS to make spi flash support
optional.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-11-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add machine identification support based on the
zynqmp_get_silicon_idcode_name function and use the soc_get_machine
function of the soc uclass to get silicon idcode name for the fpga init.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Provide a static Kconfig value for the target FPGA archtitecture, as it is
done in Linux. The cpu-uclass driver will cross-check it with the value
read from PVR10 register.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-12-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
Also, get rid of the hardcoded value in icache_disable().
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
Replace CONFIG_ICACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports
the "wic" (Write to Instruction Cache) instruction. It will be used to
guard "wic" invocations in microblaze cache code.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.
Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add support to switch to EL1 and load an EL1 app from U-Boot which is
executing at EL2 or EL3 in aarch64 mode.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220506055345.1921-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.
The Linux DP driver expects the DP to be using the following PLL config:
- DP video PLL should use the VPLL (0x0)
- DP audio PLL should use the RPLL (0x3)
- DP system time clock PLL should use RPLL (0x3)
Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
This patch fixes the DP audio and video PLL configurations for the
zynqmp-zcu102-revA evaluation board.
The Linux DP driver expects the DP to be using the following PLL config:
- DP video PLL should use the VPLL (0x0)
- DP audio PLL should use the RPLL (0x3)
Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com
This patch fixes the DP audio and video PLL configurations
for the zynqmp-zcu106-revA evaluation board.
The Linux DP driver expects the DP to be using the following PLL config:
- DP video PLL should use the VPLL (0x0)
- DP audio PLL should use the RPLL (0x3)
Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.
The Linux DP driver expects the DP to be using the following PLL config:
- DP video PLL should use the VPLL (0x0)
- DP audio PLL should use the RPLL (0x3)
Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com
board_get_usable_ram_top() was designed for getting the top most location
for U-Boot allocation that's why function itself supports via total_size
parameter to find out where the right location for U-Boot is.
But function itself is also reused by different (EFI) which is passing
total_size as 0 to find out where the usable ram top is. For this case
doesn't make sense (a waste time) to call any lmb functions.
That's why simply return gd->ram_top.
And gd->ram_top is filled already based on previous call for U-Boot iself.
The same solution is also used by stm32mp by commit 92b611e8b0 ("stm32mp:
correctly handle board_get_usable_ram_top(0)") and commit c8510e397f
("stm32mp: Fix board_get_usable_ram_top()").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com
Since versal has CONFIG_COUNTER_FREQUENCY, so use it. And
COUNTER_FREQUENCY will be dropped.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Xilinx has been acquired by AMD that's why emails should be also updated.
The patch is updating .mailmap file and also MAINTAINERS files as was done
by commit 5cd1ecb994 ("ppc: qemu: Update MAINTAINERS for correct email
address").
The rest of my emails are not going to change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add a structure which defines the information that is needed for
executing capsule updates on a platform. Some information in the
structure like the dfu string is used for making the update process
more robust while some information like the per platform image GUIDs
is used for fixing issues. Initialise this structure in the board
file, and use the information for the capsule updates.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
