Commit graph

11 commits

Author SHA1 Message Date
Kim Phillips
b211575740 mpc83xx: bump loadaddr over fdtaddr to 0x500000
this seems as a good compromise between human memory, typing,
and last but not least, to accommodate for current and future kernel bloat.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Dave Liu <daveliu@freescale.com>
2008-04-25 10:54:06 -05:00
Dave Liu
2000784818 mpc83xx: Fix the SATA clock setting of 837x targets
Currently the SATA controller clock is configured as CSB clock,
usually the CSB clock is 400/333/266MHz.

However, The SATA IP block is only guaranteed to operate up to
200 MHz as stated in the HW spec.

The bug is reported by Joe D'Abbraccio <ljd015@freescale.com>

This patch makes the SATA clock as half of CSB clock.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-04-11 17:46:17 -05:00
Kim Phillips
730e792926 mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boards
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 14:31:23 -05:00
Anton Vorontsov
18e69a35ef 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role
Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:19:39 -05:00
Scott Wood
a7ba32d480 mpc83xx: Set PCI I/O bus-address base to zero.
The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.

Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-03-25 19:16:48 -05:00
Anton Vorontsov
aabce7fb50 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards
This is primarily for the early console support.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
2bd7460e92 83xx: initialize serdes for MPC837XRDB boards
On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
46a3aeea73 83xx: nand support for MPC837XRDB boards
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:44 -05:00
Timur Tabi
89c7784ed9 83xx: Add Vitesse VSC7385 firmware uploading
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:43 -05:00
Kim Phillips
270fe261b7 mpc83xx: make dtb basename file references equal those of linux
the dts file basenames were updated in linux - this helps avoid
inadvertently loading any old dtbs laying around.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-07 12:47:11 -06:00
Kim Phillips
5e918a98c2 Add support for the MPC837xERDB
MPC837xERDB board support includes:
* DDR2 330MHz hardcoded (soldered on the board)
* Local Bus NOR Flash
* I2C, UART and RTC
* eTSEC RGMII (TSEC0 - RTL8211B with MII;
*	       TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware
*		       load)

Signed-off-by: Kevin Lam <kevin.lam@freescale.com>
Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-01-16 12:32:39 -06:00