Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 08:01:08 +00:00
Code Issues Projects Releases Packages Wiki Activity

mpc83xx: Fix the SATA clock setting of 837x targets

Browse source 
Currently the SATA controller clock is configured as CSB clock,
usually the CSB clock is 400/333/266MHz.

However, The SATA IP block is only guaranteed to operate up to
200 MHz as stated in the HW spec.

The bug is reported by Joe D'Abbraccio <ljd015@freescale.com>

This patch makes the SATA clock as half of CSB clock.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Dave Liu 2008-04-03 16:28:29 +08:00 committed by Kim Phillips
parent 1ac4f320bf
commit 2000784818
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
include/configs/MPC837XEMDS.h
View file

@ -96,7 +96,7 @@
*/
#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */
#define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
/*
* System IO Config

2
include/configs/MPC837XERDB.h
View file

@ -108,7 +108,7 @@
/* System Clock Configuration Register */
#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
#define CFG_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config