mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
83xx: Add Vitesse VSC7385 firmware uploading
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Timur Tabi
Kim Phillips
parent
b55d98c6d5
commit
89c7784ed9
6 changed files with 198 additions and 73 deletions
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@ -28,6 +28,7 @@
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#endif
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#include <pci.h>
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#include <mpc83xx.h>
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#include <vsc7385.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -98,6 +99,26 @@ void pci_init_board(void)
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mpc83xx_pci_init(1, reg, warmboot);
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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@ -25,6 +25,7 @@
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <vsc7385.h>
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#ifdef CONFIG_PCI
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#include <asm/mpc8349_pci.h>
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#include <pci.h>
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@ -177,7 +178,7 @@ int checkboard(void)
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*/
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int misc_init_f(void)
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{
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#ifdef CONFIG_VSC7385
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#ifdef CONFIG_VSC7385_ENET
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volatile u32 *vsc7385_cpuctrl;
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/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
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@ -239,6 +240,8 @@ int misc_init_f(void)
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* Make sure the EEPROM has the HRCW correctly programmed.
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* Make sure the RTC is correctly programmed.
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*
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@ -250,6 +253,8 @@ int misc_init_f(void)
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*
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* This function makes sure that the I2C EEPROM is programmed
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* correctly.
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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@ -375,6 +380,14 @@ int misc_init_r(void)
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i2c_set_bus_num(orig_bus);
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#endif
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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@ -16,6 +16,8 @@
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#include <i2c.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <vsc7385.h>
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#if defined(CFG_DRAM_TEST)
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int
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@ -56,11 +58,6 @@ testdram(void)
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}
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#endif
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int board_early_init_f(void)
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{
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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@ -135,6 +132,26 @@ int checkboard(void)
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return 0;
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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@ -38,6 +38,14 @@
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#define CONFIG_PCI
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#define CONFIG_83XX_GENERIC_PCI
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#define CONFIG_MISC_INIT_R
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/*
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* On-board devices
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*/
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#define CONFIG_VSC7385_ENET
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#ifdef CFG_66MHZ
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#elif defined(CFG_33MHZ)
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@ -64,6 +72,22 @@
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#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* Device configurations
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*/
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* DDR Setup
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*/
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@ -214,20 +238,25 @@
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#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
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#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
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#define CFG_VSC7385_BASE 0xF0000000
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#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
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#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
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#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
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#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
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#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
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/* local bus read write buffer mapping */
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#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
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#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
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#define CFG_LBLAWBAR3_PRELIM 0xFA000000
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#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
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/* Vitesse 7385 */
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#define CFG_VSC7385_BASE 0xF0000000
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#ifdef CONFIG_VSC7385_ENET
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#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
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#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
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#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
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#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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@ -263,13 +292,6 @@
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/* TSEC */
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
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#define CFG_TSEC2_OFFSET 0x25000
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#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
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#define CONFIG_NET_MULTI
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/*
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* General PCI
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* Addresses are mapped 1-1.
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@ -288,26 +310,31 @@
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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/*
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* TSEC configuration
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_MULTI
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#define CONFIG_GMII /* MII PHY management */
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CFG_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x1c
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#endif
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0x1c
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#define TSEC2_PHY_ADDR 4
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define CFG_TSEC2_OFFSET 0x25000
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#define TSEC2_PHY_ADDR 4
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC2_PHYIDX 0
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#endif
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC1"
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@ -496,10 +523,13 @@
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*/
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:E0:0C:00:95:01
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH0
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#endif
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#ifdef CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
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#endif
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#define CONFIG_IPADDR 10.0.0.2
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#define CONFIG_SERVERIP 10.0.0.1
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@ -68,12 +68,16 @@
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#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
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#define CONFIG_MISC_INIT_F
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#define CONFIG_MISC_INIT_R
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/* On-board devices */
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/*
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* On-board devices
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*/
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#ifdef CONFIG_MPC8349ITX
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#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
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#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
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#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
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#endif
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#define CONFIG_PCI
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@ -88,9 +92,6 @@
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/* I2C */
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#ifdef CONFIG_HARD_I2C
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#define CONFIG_MISC_INIT_F
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#define CONFIG_MISC_INIT_R
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
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#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFEFFE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* BRx, ORx, LBLAWBARx, and LBLAWARx
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*/
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@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385
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#define CFG_VSC7385_BASE 0xF8000000
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#ifdef CONFIG_VSC7385_ENET
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#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
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#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
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OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
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@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CFG_TSEC2_OFFSET 0x25000
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#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
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#define TSEC2_PHY_ADDR 4
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#define TSEC2_PHYIDX 0
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#define TSEC2_FLAGS TSEC_GIGABIT
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@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
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*/
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_TSEC1
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#ifdef CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
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#endif
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#ifdef CONFIG_TSEC2
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#ifdef CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
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#endif
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@ -32,6 +32,14 @@
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#define CONFIG_PCI 1
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#define CONFIG_MISC_INIT_R
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/*
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* On-board devices
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*/
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#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
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#define CONFIG_VSC7385_ENET
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/*
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* System Clock Setup
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*/
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@ -117,6 +125,22 @@
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*/
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#define CFG_IMMR 0xE0000000
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/*
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* Device configurations
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*/
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* DDR Setup
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*/
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@ -251,15 +275,19 @@
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/* Vitesse 7385 */
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#define CFG_VSC7385_BASE 0xF0000000
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/* VSC7385 Gigabit Switch support */
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#define CONFIG_VSC7385_ENET
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#ifdef CONFIG_VSC7385_ENET
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#define CFG_BR2_PRELIM 0xf0000801 /* Base address */
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#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
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#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
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#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
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#endif
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/*
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* Serial Port
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*/
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@ -324,43 +352,43 @@
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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/*
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
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#define CFG_TSEC2_OFFSET 0x25000
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#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
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#ifdef CONFIG_TSEC_ENET
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_NET_MULTI
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#define CONFIG_GMII /* MII PHY management */
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#define CONFIG_TSEC1
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CFG_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 0x1c
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TSEC2
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define CFG_TSEC2_OFFSET 0x25000
|
||||
#define TSEC2_PHY_ADDR 0x1c
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_PHYIDX 0
|
||||
#endif
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
|
@ -529,10 +557,13 @@
|
|||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
||||
#define CONFIG_ETHADDR 00:04:9f:ef:04:01
|
||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
|
||||
#ifdef CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHADDR 00:04:9f:ef:04:01
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 10.0.0.2
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
|
|
|
|||
Loading…
Reference in a new issue