Commit graph

70407 commits

Author SHA1 Message Date
Greg Gallagher
9119800591 board: atmel: Add SAMA5D27 giant board
Giant board is a tiny SBC based on the Adafruit Feather form factor,
created by groboards it contains a SAMA5D2 processor (SAMA5D27),
128 MB of RAM and a microSD card for storage.

Signed-off-by: Greg Gallagher <greg@embeddedgreg.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
1ae8f0a3b2 net: macb: take into account all RGMII interface types
Take into account all RGMII interface types. Depending on it
the RGMII PHY's timings are setup.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
3d3475c8b7 net: macb: add support for sama7g5 emac
Add support for SAMA7G5 EMAC.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
8c0483ecbf net: macb: add support for sama7g5 gmac
Add support for SAMA7G5 GMAC.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
96449581b3 net: macb: check clk_set_rate return value to be negative
clk_set_rate() returns the set rate in case of success and a
negative number in case of failure. Consider failure only the
negative numbers.

Fixes: 3ef64444de ("dm: net: macb: Implement link speed change callback")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
bb890f75d5 net: macb: add user io config data structure
Different implementation of USER IO register needs different
mapping for bit fields of this register. Add implementation
for this and, since clken is part of USER IO and it needs to
be activated based on per SoC capabilities, add caps in
macb_config where clken specific information needs to be filled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-22 15:09:59 +02:00
Kai Stuhlemmer (ebee Engineering)
3270c47b39 sam9x60.h: Fix Galois Field Table offsets
Because ATMEL_BASE_ROM is defined to 0x100000, it already points
to the begin of the index table for 512 byte sectors correction.
Thus its offset must be zero and the index of the table for 1024
byte sectors must start at offset 0x8000.

Signed-off-by: Kai Stuhlemmer (ebee Engineering) <kai.stuhlemmer@ebee.de>
[ta: update commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-01-22 15:09:59 +02:00
Tudor Ambarus
786f888b74 sama5d3: Fix Galois Field Table offsets
Offsets are described in the datasheet at section:
"11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction".

For testing I "injected" bit flips into u-boot NAND memory area,
and then read back. PMECC could not correct the errors. With the
offsets updated everything is fine.

Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-01-22 15:09:59 +02:00
Tudor Ambarus
58b1d680d1 configs: at91: Fix wrong definitions for CONFIG_PMECC_CAP
When CONFIG_ATMEL_NAND_HW_PMECC is set, CONFIG_PMECC_CAP defaults
to the value of 2. At the conversion to Kconfig for the PMECC config
values, some boards/defconfigs were wrongly configured.
Update CONFIG_PMECC_CAP to the PMECC_CAP value before the conversion.

Fixes: 49ad40298c ("ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-01-22 15:09:59 +02:00
Tudor Ambarus
6f889819f3 configs: at91: Fix the involuntarily disablement of NAND PMECC
SPL_GENERATE_ATMEL_PMECC_HEADER selects:
ATMEL_NAND_HWECC [=y] && ATMEL_NAND_HW_PMECC [=y].

With the removal of SPL_GENERATE_ATMEL_PMECC_HEADER,
ATMEL_NAND_HW_PMECC and ATMEL_NAND_HWECC were no longer
selected. Also, when the SPL_GENERATE_ATMEL_PMECC_HEADER was removed,
the configs were not updated using savedefconfig, thus the
'commit d168bcb6fe ("configs: Resync with savedefconfig")'
further removes the CONFIG_PMECC_CAP value.

Update defconfigs and add CONFIG_ATMEL_NAND_HW_PMECC,
which selects ATMEL_NAND_HWECC, in order to restore NAND PMECC
support. Restore CONFIG_PMECC_CAP value.

Fixes: 57f76c2a47 ("configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-01-22 15:09:59 +02:00
Eugen Hristev
417eca09bf pinctrl: at91-pio4: implement drive strength support
Implement drive strength support, by preserving the same bindings
as in Linux.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-22 15:09:59 +02:00
Eugen Hristev
864a4144ba pinctrl: at91-pio4: convert to dev_read_prop
Use dev_read_prop instead of using the fdt_read_property which
reads from the GD struct's fdt.
This way the node is accessed via the device config instead of the
global struct, which makes code more portable and GD independent.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-22 15:09:59 +02:00
Eugen Hristev
63c27c3e66 dt-bindings: pinctrl: at91-pio4: add property for drive strength
Add drive strength property which is equivalent with the one in Linux

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-22 15:09:59 +02:00
Eugen Hristev
7cdcf0cb69 dt-bindings: pinctrl: at91-pio4: update license to SPDX style
Update license header to SPDX style

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-22 15:09:59 +02:00
Claudiu Beznea
36dfddc553 net: phy: micrel: fix typo
Fix typo.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-19 10:11:14 +02:00
Claudiu Beznea
c6df0e2ffd net: phy: micrel: add support for DLL setup on ksz9131
Add support for DLL setup on KSZ9131.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-01-19 10:11:14 +02:00
Tom Rini
ae3d8b6c40 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- R-Car pinctrl updates
2021-01-18 12:38:22 -05:00
Tom Rini
59e4e391df Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
  - Select TIMER_EARLY to avoid infinite recursion for Trace.
2021-01-18 08:04:28 -05:00
Tom Rini
b5b0237d02 Pull request for documentation tag doc-2021-04-rc1
* document man-page base command
 * move README.fdt-overlays to HTML documentation
 * add synopsis for pstore command
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Merge tag 'doc-2021-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for documentation tag doc-2021-04-rc1

* document man-page base command
* move README.fdt-overlays to HTML documentation
* add synopsis for pstore command
2021-01-18 08:04:05 -05:00
Tom Rini
19c5fdffdc Merge branch '2021-01-16-assorted-improvements'
- Assorted testing improvements and fixes
- Assorted code cleanups
2021-01-18 07:55:54 -05:00
Lad Prabhakar
67704d6dfb ARM: dts: renesas: Remove leading 0x from rpc node
Remove the leading "0x" from rpc node to fix the below dtc warning:

Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Lad Prabhakar
8096e2426d pinctrl: renesas: Implement get_pin_muxing() callback
Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Lad Prabhakar
cc6aa80dd1 pinctrl: renesas: Make sure the pin type is updated after setting the MUX
By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).

So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.

This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.

This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-01-18 13:29:12 +01:00
Padmarao Begari
9e550e1830 doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:39 +08:00
Padmarao Begari
64413e1b7c riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
dd4ee416a6 riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
2f27c9219e clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
1b4593826c net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
6f0b237372 net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.

The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-18 11:06:38 +08:00
Padmarao Begari
5af3574f6a riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:38 +08:00
Pragnesh Patel
bc8d12bfd8 riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:32 +08:00
Pragnesh Patel
a80f85138c trace: select TIMER_EARLY to avoid infinite recursion
When tracing functions is enabled this adds calls to
__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
functions.

__cyg_profile_func_enter() and __cyg_profile_func_exit() invoke
timer_get_us() to record the entry and exit time.

initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so
timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
indefinite recursion.

So select TIMER_EARLY when tracing got enabled.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:32 +08:00
Sean Anderson
8f78e52794 riscv: Add support for SPI on Kendryte K210
This enables configs necessary for using SPI. The environment is saved to
the very end of SPI flash. This is unlikely to be overwritten unless the
entire flash is reprogrammed.

This also supplies a default bootcommand. It loads an image and device tree
from the first partition of the MMC. This is a minimal/least effort
bootcmd, so suggestions (especially in the form of patches) are welcome. I
didn't set up distro boot because I think it is unlikely that any
general-purpose linux distros will ever be ported to this board.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Chrstopher Obbard <obbardc@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:26 +08:00
Atish Patra
24c5689447 doc: qemu-riscv: Fix opensbi build instructions
Latest opensbi uses generic platform for Qemu. Update the build
instructions.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-18 11:06:20 +08:00
Ravik Hasija
ad80a8d087 cmd: disk: Remove fit_print_contents API
fit_print_contents prints similar fit information as printed in bootm stages.
Removing this API reduces redundancy & provides improvement in boottime.

Signed-off-by: Ravik Hasija <rahasij@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Patrick Delaunay
6205bbb1e0 lib: cosmetic update of CONFIG_LIB_ELF description
Change 2 typo error in CONFIG_LIB_ELF description:
- Supoort => Support
- fir => for

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
c548a3886e test: unit test for pr_err(), pr_cont()
Provide a unit test for printing via pr_err() and pr_cont().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
2496796587 log: provide missing macros
With commit d094a0734c ("log: allow for message continuation") we have
defined a special log level and category for message continuation. Let's
have a macro for using these.

If logging is enabled log_cont() will create a continuation log output with
the same logging level and category as the previous message.

If logging is not enabled, log_cont() will print like printf().

Provide macros for logging levels LOG_EMERG, LOG_ALERT, LOG_CRIT.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
5176365a6b log: make debug_cond() function like
Change debug_cond() such that it can be used instead of a function like
debug().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
f5abd8a616 ram: k3-j721e: rename BIT_MASK()
The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid
name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h
to LPDDR4_BIT_MASK().

Remove superfluous parantheses.
Remove superfluous comparison to 0.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
bcb0203c61 mtd: misplaced log.h and dm/devres.h
log.h and dm/devres.h are U-Boot includes. So placing them
behind #ifndef __UBOOT__ does not make any sense.

Fixes: f7ae49fc4f ("common: Drop log.h from common header")
Fixes: 61b29b8268 ("dm: core: Require users of devres to include the header")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
986c841c8b lib: zlib: our putc() takes only one argument
In contrast to the C99 standard [1] our putc() takes only one argument.

[1] ISO/IEC 9899:1999

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
834427d463 lib: zlib: include ctype.h
Our ctype.h is in include/linux/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-16 19:17:11 -05:00
Heinrich Schuchardt
3e50deece0 lib: aes: build failure with DEBUG=1
Building fails with DEBUG=1:

lib/aes.c: In function ‘debug_print_vector’:
lib/aes.c:622:45: error:
cast from pointer to integer of different size
[-Werror=pointer-to-int-cast]
  622 |  printf("%s [%d] @0x%08x", name, num_bytes, (u32)data);

Pointers can only be cast to (uintptr_t). But anyway we have
%p for printing pointers.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Peng Fan
0634b374ae armv8: Makefile: build cache files when needed
If no need cache support, not build the cache files, such as in SPL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-16 19:17:11 -05:00
Peng Fan
52e77726ef common: Makefile: drop duplicated line
obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o is there,
no need obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 14:49:09 -05:00
Florian Klink
1d55eb1544 dts: Log name of expected .dtb file
Make it more obvious what .dts file was expected by the build system.

When adding support for a new board, I kept getting this error message,
assuming I passed a wrong DEVICE_TREE parameter.

However, what was really the mistake was that the entry in
`arch/arm/dts/Makefile` was missing, and u-boot didn't like not being
able to find the .dtb file that should have been produced.

Simply logging the expected .dtb file name should make it easier to spot
such mistakes.

Signed-off-by: Florian Klink <flokli@flokli.de>
2021-01-16 14:49:09 -05:00
Pali Rohár
83a287a613 bootmenu: Allow to quit it via ESC/CTRL+C
When ESC/CTRL+C is pressed interrupt bootmenu and jump into U-Boot console.
As the last entry in bootmenu is always U-Boot console just choose the last
entry when ESC or CTRL+C is pressed.

ESC key is detected when either no other character appears after '\e'
within 10ms or when non-'[' appears after '\e'.

It is useful when bootmenu is part of boot process and you want to
interrupt boot process by scripts which control U-Boot (serial) console.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 14:49:09 -05:00
Patrick Delaunay
976a68a20d string: Use memcpy() within memmove() when we can
A common use of memmove() can be handled by memcpy(). Also memcpy()
includes an optimization for large sizes: it copies a word at a time. So
we can get a speed-up by calling memcpy() to handle our move in this case.

Update memmove() to call also memcpy() if the source don't overlap
the destination (src + count <= dest).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-01-16 14:49:09 -05:00
Vabhav Sharma
67b2ed0243 drivers: serial: probe all uart devices
U-Boot DM model probe only single device at a time
which is enabled and configured using device tree
or platform data method.

PL011 UART IP is SBSA compliant and firmware does the
serial port set-up, initialization and let the kernel use
UART port for sending and receiving characters.

Normally software talk to one serial port time but some
LayerScape platform require all the UART devices enabled
in Linux for various use case.

Adding support to probe all enabled serial devices like SBSA
compliant PL011 UART ports probe and initialization by firmware.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-01-16 14:49:09 -05:00