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net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb hardware compatibility and it is configured with structure macb_config in the driver. The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
This commit is contained in:
Padmarao Begari
Andes
parent
5af3574f6a
commit
6f0b237372
2 changed files with 119 additions and 16 deletions
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@ -83,7 +83,16 @@ struct macb_dma_desc {
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u32 ctrl;
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};
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#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
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struct macb_dma_desc_64 {
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u32 addrh;
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u32 unused;
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};
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#define HW_DMA_CAP_32B 0
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#define HW_DMA_CAP_64B 1
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#define DMA_DESC_SIZE 16
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#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
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#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
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#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
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#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
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@ -137,6 +146,7 @@ struct macb_device {
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struct macb_config {
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unsigned int dma_burst_length;
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unsigned int hw_dma_cap;
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int (*clk_init)(struct udevice *dev, ulong rate);
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};
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@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
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#if defined(CONFIG_CMD_NET)
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static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
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{
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return (struct macb_dma_desc_64 *)((void *)desc
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+ sizeof(struct macb_dma_desc));
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}
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static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
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ulong addr)
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{
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struct macb_dma_desc_64 *desc_64;
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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desc_64 = macb_64b_desc(desc);
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desc_64->addrh = upper_32_bits(addr);
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}
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desc->addr = lower_32_bits(addr);
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}
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static int _macb_send(struct macb_device *macb, const char *name, void *packet,
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int length)
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{
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@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
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macb->tx_head++;
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}
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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tx_head = tx_head * 2;
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macb->tx_ring[tx_head].ctrl = ctrl;
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macb->tx_ring[tx_head].addr = paddr;
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macb_set_addr(macb, &macb->tx_ring[tx_head], paddr);
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barrier();
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macb_flush_ring_desc(macb, TX);
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macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
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@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
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unsigned int new_tail)
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{
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unsigned int i;
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unsigned int count;
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i = macb->rx_tail;
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macb_invalidate_ring_desc(macb, RX);
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while (i > new_tail) {
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macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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count = i * 2;
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else
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count = i;
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macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
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i++;
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if (i > MACB_RX_RING_SIZE)
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i = 0;
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}
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while (i < new_tail) {
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macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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count = i * 2;
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else
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count = i;
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macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
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i++;
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}
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@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar **packetp)
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void *buffer;
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int length;
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u32 status;
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u8 flag = false;
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macb->wrapped = false;
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for (;;) {
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macb_invalidate_ring_desc(macb, RX);
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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next_rx_tail = next_rx_tail * 2;
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if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
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return -EAGAIN;
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status = macb->rx_ring[next_rx_tail].ctrl;
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if (status & MACB_BIT(RX_SOF)) {
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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next_rx_tail = next_rx_tail / 2;
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flag = true;
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}
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if (next_rx_tail != macb->rx_tail)
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reclaim_rx_buffers(macb, next_rx_tail);
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macb->wrapped = false;
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@ -426,11 +476,22 @@ static int _macb_recv(struct macb_device *macb, uchar **packetp)
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*packetp = buffer;
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}
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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if (!flag)
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next_rx_tail = next_rx_tail / 2;
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}
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if (++next_rx_tail >= MACB_RX_RING_SIZE)
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next_rx_tail = 0;
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macb->next_rx_tail = next_rx_tail;
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return length;
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} else {
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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if (!flag)
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next_rx_tail = next_rx_tail / 2;
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flag = false;
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}
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if (++next_rx_tail >= MACB_RX_RING_SIZE) {
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macb->wrapped = true;
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next_rx_tail = 0;
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@ -718,6 +779,7 @@ static int gmac_init_multi_queues(struct macb_device *macb)
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{
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int i, num_queues = 1;
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u32 queue_mask;
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unsigned long paddr;
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/* bit 0 is never set but queue 0 always exists */
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queue_mask = gem_readl(macb, DCFG6) & 0xff;
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@ -731,10 +793,18 @@ static int gmac_init_multi_queues(struct macb_device *macb)
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macb->dummy_desc->addr = 0;
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flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
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ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
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paddr = macb->dummy_desc_dma;
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for (i = 1; i < num_queues; i++)
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gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
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for (i = 1; i < num_queues; i++) {
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gem_writel_queue_TBQP(macb, lower_32_bits(paddr), i - 1);
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gem_writel_queue_RBQP(macb, lower_32_bits(paddr), i - 1);
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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gem_writel_queue_TBQPH(macb, upper_32_bits(paddr),
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i - 1);
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gem_writel_queue_RBQPH(macb, upper_32_bits(paddr),
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i - 1);
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}
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}
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return 0;
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}
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@ -760,6 +830,9 @@ static void gmac_configure_dma(struct macb_device *macb)
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dmacfg &= ~GEM_BIT(ENDIA_DESC);
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dmacfg &= ~GEM_BIT(ADDR64);
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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dmacfg |= GEM_BIT(ADDR64);
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gem_writel(macb, DMACFG, dmacfg);
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}
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@ -775,6 +848,7 @@ static int _macb_init(struct macb_device *macb, const char *name)
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unsigned long paddr;
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int ret;
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int i;
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int count;
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/*
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* macb_halt should have been called at some point before now,
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@ -786,20 +860,28 @@ static int _macb_init(struct macb_device *macb, const char *name)
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for (i = 0; i < MACB_RX_RING_SIZE; i++) {
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if (i == (MACB_RX_RING_SIZE - 1))
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paddr |= MACB_BIT(RX_WRAP);
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macb->rx_ring[i].addr = paddr;
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macb->rx_ring[i].ctrl = 0;
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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count = i * 2;
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else
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count = i;
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macb->rx_ring[count].ctrl = 0;
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macb_set_addr(macb, &macb->rx_ring[count], paddr);
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paddr += macb->rx_buffer_size;
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}
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macb_flush_ring_desc(macb, RX);
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macb_flush_rx_buffer(macb);
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for (i = 0; i < MACB_TX_RING_SIZE; i++) {
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macb->tx_ring[i].addr = 0;
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
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count = i * 2;
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else
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count = i;
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macb_set_addr(macb, &macb->tx_ring[count], 0);
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if (i == (MACB_TX_RING_SIZE - 1))
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macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
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macb->tx_ring[count].ctrl = MACB_BIT(TX_USED) |
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MACB_BIT(TX_WRAP);
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else
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macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
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macb->tx_ring[count].ctrl = MACB_BIT(TX_USED);
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}
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macb_flush_ring_desc(macb, TX);
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@ -812,8 +894,12 @@ static int _macb_init(struct macb_device *macb, const char *name)
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gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
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#endif
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macb_writel(macb, RBQP, macb->rx_ring_dma);
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macb_writel(macb, TBQP, macb->tx_ring_dma);
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macb_writel(macb, RBQP, lower_32_bits(macb->rx_ring_dma));
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macb_writel(macb, TBQP, lower_32_bits(macb->tx_ring_dma));
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if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
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macb_writel(macb, RBQPH, upper_32_bits(macb->rx_ring_dma));
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macb_writel(macb, TBQPH, upper_32_bits(macb->tx_ring_dma));
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}
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if (macb_is_gem(macb)) {
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/* Initialize DMA properties */
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@ -1217,6 +1303,7 @@ static int macb_enable_clk(struct udevice *dev)
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static const struct macb_config default_gem_config = {
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.dma_burst_length = 16,
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.hw_dma_cap = HW_DMA_CAP_32B,
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.clk_init = NULL,
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};
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@ -1227,8 +1314,8 @@ static int macb_eth_probe(struct udevice *dev)
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const char *phy_mode;
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int ret;
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phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
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NULL);
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phy_mode = dev_read_prop(dev, "phy-mode", NULL);
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if (phy_mode)
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macb->phy_interface = phy_get_interface_by_name(phy_mode);
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if (macb->phy_interface == -1) {
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@ -1304,13 +1391,21 @@ static int macb_eth_of_to_plat(struct udevice *dev)
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return macb_late_eth_of_to_plat(dev);
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}
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static const struct macb_config microchip_config = {
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.dma_burst_length = 16,
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.hw_dma_cap = HW_DMA_CAP_64B,
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.clk_init = NULL,
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};
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static const struct macb_config sama5d4_config = {
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.dma_burst_length = 4,
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.hw_dma_cap = HW_DMA_CAP_32B,
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.clk_init = NULL,
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};
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static const struct macb_config sifive_config = {
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.dma_burst_length = 16,
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.hw_dma_cap = HW_DMA_CAP_32B,
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.clk_init = macb_sifive_clk_init,
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};
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@ -1324,6 +1419,8 @@ static const struct udevice_id macb_eth_ids[] = {
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{ .compatible = "cdns,zynq-gem" },
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{ .compatible = "sifive,fu540-c000-gem",
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.data = (ulong)&sifive_config },
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{ .compatible = "microchip,mpfs-mss-gem",
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.data = (ulong)µchip_config },
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{ }
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};
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@ -768,5 +768,11 @@
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#define GEM_RX_CSUM_CHECKED_MASK 2
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#define gem_writel_queue_TBQP(port, value, queue_num) \
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writel((value), (port)->regs + GEM_TBQP(queue_num))
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#define gem_writel_queue_TBQPH(port, value, queue_num) \
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writel((value), (port)->regs + GEM_TBQPH(queue_num))
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#define gem_writel_queue_RBQP(port, value, queue_num) \
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writel((value), (port)->regs + GEM_RBQP(queue_num))
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#define gem_writel_queue_RBQPH(port, value, queue_num) \
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writel((value), (port)->regs + GEM_RBQPH(queue_num))
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#endif /* __DRIVERS_MACB_H__ */
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