Commit graph

24 commits

Author SHA1 Message Date
Simon Glass
8f1f374f63 x86: galileo: Use devicetree for SMBIOS settings
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 10:18:20 +08:00
Neil Armstrong
51e4e3e5d0 x86: dts: switch spi-flash to jedec, spi-nor compatible
The x86 code and DT uses "spi-flash" to detect a flash node, switch to
"jedec,spi-nor" in the DTS files and in fdtdec by switching the
GENERIC_SPI_FLASH value to to jedec,spi-nor.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Bin Meng
b37b7b2063 x86: Switch to use DM sysreset driver
This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
bc728b1bc0 x86: irq: Remove chipset specific irq router drivers
At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use
the common one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Bin Meng
0ac8d5e552 x86: galileo: Enable CPU driver
Add a cpu node in the device tree and enable CPU driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
ce8dd77d99 x86: dts: Update to include ACTL register details
This updates all x86 boards that currently have IRQ router in the
dts files to include ACTL register details.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
3ddc1c7bd3 x86: ich6_gpio: Convert to use proper DM API
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.

Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
1f9eb59d27 spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:20 +08:00
Bin Meng
81aaa3d9fc x86: Correct spi node alias
With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Simon Glass
117bfc7fbe dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
f2b85ab5e6 dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Bin Meng
c5c5c201fe x86: Fix PCI UART compatible string for crownbay and galileo
With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:41 +08:00
Bin Meng
80af39842e x86: Convert to use driver model timer
Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
06f16c4148 x86: galileo: Enable mrc cache
Now that we have added MRC cache on quark support codes,
enable it on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
5bf0f7f65d x86: galileo: Add PCIe root port IRQ routing
Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:53 -06:00
Bin Meng
31b5aebd5e x86: Convert to use driver model pci on quark/galileo
Move to driver model pci for Intel quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
93f8a31186 x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-28 10:36:22 -06:00
Bin Meng
05b98ec346 x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Bin Meng
0a9bb489bf x86: Add alias for SPI node in the board dts
Since Intel ICH SPI driver has been converted to driver model, we need
add an alias for SPI node in the board dts files otherwise SPI flash
won't be detected due to 'invalid bus' error.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Bin Meng
728b393f3b x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
d8b1d22512 x86: galileo: Add GPIO support
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:45 -07:00
Bin Meng
20c34115d6 x86: quark: Call MRC in dram_init()
Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:44 -07:00
Bin Meng
afee3fb8c8 x86: Add basic Intel Galileo board support
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:41 -07:00