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Author SHA1 Message Date
Kumar Gala
79e4e6480b powerpc/8xxx: Enabled hwconfig for memory interleaving
Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
hwconfig parameters. The syntax is

    setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>"

The mode values for memory controller interleaving are
    cacheline
    page
    bank
    superbank

The mode values for bank interleaving are
    cs0_cs1
    cs2_cs3
    cs0_cs1_and_cs2_cs3
    cs0_cs1_cs2_cs3

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:16:08 -05:00
Kumar Gala
fd3c9befa8 powerpc/p4080: Add workaround for erratum CPU22
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
61054ffa16 powerpc/p4080: Add workaround for errata SERDES8
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
34a8258fea powerpc/p4080: Add support for initializing SERDES
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.

Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:57 -05:00
Kumar Gala
db977abfc8 powerpc/85xx: Add support to initialize LIODN registers and portals
On the new QorIQ/CoreNet based platforms we need to initialize the
"portals" as access into the Data Path subystem as well as Logical IO
Device Numbers (LIODN) that are used for the IOMMU (PAMU).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
Kumar Gala
6aba33e939 powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers.  Enable that cache as well as add information into the
device tree about it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 13:07:56 -05:00
york
a3f18529ec powerpc/85xx: Move INIT_RAM_ADDR physical address to 36-bit space
If 36-bit physical address is used, move the INIT_RAM_ADDR to higher
address. This frees the low 4GB address space for better use.

Signed-off-by: York Sun <yorksun@freescale.com>
2010-07-26 13:07:49 -05:00
Kumar Gala
ebd7cb0ba9 powerpc/fsl_fman: Add initial fman immap structures
Add basic structures for Frame Manager on P4080/P3041/P5020 devices

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 08:07:47 -05:00
Kumar Gala
9ab87d04a8 powerpc/85xx: Add additional p4080 platform related defines/structs
* Added PCIE4 address, offset, DEVDISR & LAW target ID
* Added new p4080 DDR registers and defines to immap
* Add missing corenet platform DEVDISR related defines
* Updated ccsr_gur to include LIODN registers
* Add RCWSR defines
* Added Basic qman, pme, bman immap structs
* Added SATA related offsets & addresses
* Added Frame Manager 1/2 offsets & addresses
* Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
* Added various offsets and addresses that where missing

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26 08:07:47 -05:00
Wolfgang Denk
47e26b1bf9 cmd_usage(): simplify return code handling
Lots of code use this construct:

	cmd_usage(cmdtp);
	return 1;

Change cmd_usage() let it return 1 - then we can replace all these
ocurrances by

	return cmd_usage(cmdtp);

This fixes a few places with incorrect return code handling, too.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-07-24 20:43:57 +02:00
Wolfgang Denk
9662317142 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-07-24 20:34:13 +02:00
Stefan Roese
be24ef6e8e ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 core
Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:55:03 +02:00
Stefan Roese
58eb869ffc ppc4xx: Add "ecctest" command to test/simulate ECC errors
This patch adds the "ecctest" command to test and simulate ECC errors
(single bit and/or double bit) while running from SDRAM. Currently only
the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).

This is done by copying and calling functions, modifying the SDRAM
controller operation mode, in internal SRAM/OCM.

For correctable ECC errors (single bit) only the status will be printed
since the DDR2 controller doesn't provide the faulting address:

=> ecctest 1000000 1
Using address 01000000 for 1 bit ECC error injection
ECC: Correctable error

Uncorrectable ECC errors (double bit) will also display the faulting
address:

=> ecctest 1000000 2
Using address 01000000 for 2 bit ECC error injection
ECC: Uncorrectable error at 0x0001000000

To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
in the board config header.

Tested on katmai and t3corp.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:54 +02:00
Stefan Roese
b995d7cb2c ppc4xx: DDR/ECC: Use correct macros to clear error status
Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.

Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:28 +02:00
Stefan Roese
897d6abc50 ppc4xx: Only define DDR2 registers for the correct PowerPC variants
Make sure that some SDRAM/DDR2 registers are only defined for the PPC
variants really implementing those registers.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:22 +02:00
Stefan Roese
eab9800182 ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values
Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-23 09:54:09 +02:00
Kumar Gala
47ec10c597 powerpc/85xx: Rework P1022 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-21 00:40:20 -05:00
Kumar Gala
af0250652a powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-21 00:40:16 -05:00
Kumar Gala
c26de2d8b1 powerpc/p3041: Add various p3041 related defines
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Kumar Gala
19dbcc96c0 powerpc/p5020: Add various p5020 related defines (and p5010)
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:19 -05:00
Emil Medve
7eda1f8eed powerpc/mpc85xx: Report FMAN # to match user manual
The user manual refers to FMAN1 and FMAN2 not 0 and 1.

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:18 -05:00
Kumar Gala
85f8cda3c2 powerpc/p4080: Add setting of clock-frequency for clockgen node
On QorIQ CoreNet based devices we have a global clocking block.  We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:41:18 -05:00
Kumar Gala
1b942f7483 powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates
Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:40:06 -05:00
Kumar Gala
6525d51fa5 powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases
Previously we used an alias the pci node to determine which node to
fixup or delete.  Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:40:06 -05:00
Kumar Gala
dd2cda3dbd powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.  Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Kumar Gala
99d9c07edc powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Wolfgang Denk
0fe247b973 Drop support for GTH board
The board maintainer states:

    The GTH board is obsolete and has not been manufactured for
    several years.
    To my knowledge, no recent U-Boot build has been tested on that
    card.

So drop support for this board.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Acked-by: Thomas Lange<thomas@corelatus.se>
2010-07-17 20:47:08 +02:00
Kumar Gala
9f43d7997e powerpc/85xx: Move p1022ds slot code into board file
The code to map SERDES configs to slot names is board specific and not
chip specific.  Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Kumar Gala
79ee344802 powerpc/85xx: Add command to report errata workarounds
Add 'errata' command to report what errata we workaround.  Report
workaround for erratum SATA-A001 on P1022/P1013.

Also sorted the CONFIG_CMD_* list.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Timur Tabi
c59e1b4d07 powerpc: add support for the Freescale P1022DS reference board
Specifics:

1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Timur Tabi
752bc33530 fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller.  Also update
the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the
LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure.

This will allow future PCI[E] code to configure the LAW target automatically,
rather than requiring each board to it for each PCI controller separately.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:10 -05:00
Kumar Gala
ae3913922a powerpc/85xx: Add support for link stack & STAC on e5500
The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
implemented in the register.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Kumar Gala
2a3a96ca5e powerpc/85xx: Add recognition of e5500 core
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
f2d9a5da29 powerpc 83xx/85xx: Merge lbc upmconfig code
Each platform had its own version of the upmconfig, despite the
init process being identical.  Now that we have a spot for common
lbc code, create a common upmconfig() there.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
199e262eb3 mpc85xx: Add reginfo command
The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
e71755f887 drivers/misc/fsl_law.c: Rearrange code to avoid duplication
The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
70e02bca6b mpc85xx: Add print_tlbcam() function
This dumps out the contents of TLB1 on 85xx-based systems.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
4e63df300f mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code.  Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Becky Bruce
f51cdaf191 83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Kumar Gala
8f3a7fa4a2 powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb
If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:08 -05:00
Kumar Gala
11beefa382 mpc8xxx: Remove cpu-handles for cpus we delete
We may have cpu-handles pointing to the cpu nodes we delete.  If so we
should delete the handles as well.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:08 -05:00
Kim Phillips
22f292c7b2 powerpc/8xxx: Add base support for the SEC4
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Kim Phillips
929a213830 powerpc/8xxx: Distinguish between incompatible SEC h/w types
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Kim Phillips
5d0c3b57b2 fdt: move fsl specific code from common fdt area to mpc8xxx/fdt.c
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:07 -05:00
Ilya Yanok
7c619ddcee mpc8308: support for Freescale MPC8308 cpu
This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-07-09 15:00:54 -05:00
Wolfgang Denk
54841ab50c Make sure that argv[] argument pointers are not modified.
The hush shell dynamically allocates (and re-allocates) memory for the
argument strings in the "char *argv[]" argument vector passed to
commands.  Any code that modifies these pointers will cause serious
corruption of the malloc data structures and crash U-Boot, so make
sure the compiler can check that no such modifications are being done
by changing the code into "char * const argv[]".

This modification is the result of debugging a strange crash caused
after adding a new command, which used the following argument
processing code which has been working perfectly fine in all Unix
systems since version 6 - but not so in U-Boot:

int main (int argc, char **argv)
{
	while (--argc > 0 && **++argv == '-') {
/* ====> */	while (*++*argv) {
			switch (**argv) {
			case 'd':
				debug++;
				break;
			...
			default:
				usage ();
			}
		}
	}
	...
}

The line marked "====>" will corrupt the malloc data structures and
usually cause U-Boot to crash when the next command gets executed by
the shell.  With the modification, the compiler will prevent this with
an
	error: increment of read-only location '*argv'

N.B.: The code above can be trivially rewritten like this:

	while (--argc > 0 && **++argv == '-') {
		char *arg = *argv;
		while (*++arg) {
			switch (*arg) {
			...

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2010-07-04 23:55:42 +02:00
Stefan Roese
4978e60584 ppc4xx: Cleanup Boot/FLASH TLB reassignment for PPC440/460
Background Info:
Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via
init.S) to speed up the boot process. In relocate_code (start.S) the
cache inhibit attribute for this TLB is set to disable cache. This is
needed for the CFI FLASH driver.

This patch now cleans this code up:
- CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not
  defined in the top of this file. This way, we can remove an ugly
  #ifdef in this code.
- Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..."
  statement with "#if defined(CONFIG_440)".
- Remove unnecessary cache invalidate calls resulting in faster bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:25 +02:00
Stefan Roese
2909ac03f4 ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:20 +02:00
Stefan Roese
e9c020df96 ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boards
As described in item  of the SDRAM initialization (chapter 22.2.9
of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The
code for this is now factored out and executed for non-SPD based boards
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:15 +02:00
Stefan Roese
066003b2c5 ppc4xx: Enable overwriting of default scan window for IBM DDR2 controller
This patch makes it possible to overwrite the default auto-calibration
scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with
board specific values. The parameters of the weak default function are
corrected as well. This way we don't need the casts any more.

This feature will be used by an upcoming PPC460GT board port.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:10 +02:00
Stefan Roese
db643773fc ppc4xx: Enable PCIe support without PCI support on PPC440/460
By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT,
PCI support (host and adapter) will not be enabled. But it's still
possible to use the U-Boot PCI infrastructure for the PCIe ports.

This configuration option is needed for a new 460GT board, which uses
PCIe but has PCI disabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:26:01 +02:00
Stefan Roese
fe7cca715c ppc4xx: Enable booting with Option E on 460EX/EXr/GT
This patch enables booting with option E on the PPC460EX/EXr/GT.
When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0.
The Software Boot Configuration Procedure is needed to engage the
PLL and perform a chip reset.

Signed-off-by: Stefan Roese <sr@denx.de>
2010-07-01 10:25:56 +02:00
Wolfgang Denk
0a9463e935 Merge branch 'master' into next 2010-06-30 01:02:11 +02:00
Michael Weiss
955ea6fc27 powerpc/bootcount: Add bootcount support for MPC512x
This also uses the breadcrumb register as on MPC5200.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-06-29 23:13:35 +02:00
Wolfgang Denk
4ccd5510e5 MPC512x: workaround data corruption for unaligned local bus accesses
Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned
local bus accesses" fixed the problem for MPC5200 only, but MPC512x is
affected as well, so apply the same fix here, too.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-06-29 14:41:37 +02:00
Wolfgang Denk
953b7e6291 Remove AmigaOneG3SE board
The AmigaOneG3SE board has been orphaned or a very long time, and
broken for more than 12 releases resp. more than 3 years.  As nobody
seems to be interested any more in this stuff we may as well ged rid
of it, especially as it clutters many areas of the code so it is a
continuous pain for all kinds of ongoing work.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-06-23 23:24:20 +02:00
Wolfgang Denk
ee80fa7b6e Get rid of bogus CONFIG_SYS_BUS_HZ and CONFIG_SYS_CONFIG_BUS_CLK definitions
CONFIG_SYS_BUS_HZ has not really been used anywhere except to be
redined as CONFIG_SYS_BUS_CLK; in addition, the mpc7448hpc2 had the
bogus CONFIG_SYS_CONFIG_BUS_CLK setting which duplicated the
funtionality.  Change all this to use CONFIG_SYS_BUS_CLK consistently.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Frank Gottschling <fgottschling@eltec.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Eran Man <eran@nbase.co.il>
Cc: Stefan Roese <sr@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
2010-06-23 23:24:11 +02:00
Wolfgang Denk
f35f3968c2 Merge branch 'master' into next 2010-06-23 21:17:29 +02:00
Wolfgang Denk
460c2ce362 MPC5200: workaround data corruption for unaligned local bus accesses
The MPC5200 has a nasty problem that will cause silent data corruption
when performing unaligned 16 or 32 byte accesses when reading from the
local bus - typically this affects reading from flash. The problem can
be easily shown:

=> md fc0c0000 10
fc0c0000: 323e4337 01626f6f 74636d64 3d72756e    2>C7.bootcmd=run
fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c     net_nfs.bootdel
fc0c0020: 61793d35 00626175 64726174 653d3131    ay=5.baudrate=11
fc0c0030: 35323030 00707265 626f6f74 3d656368    5200.preboot=ech
=> md fc0c0001 10
fc0c0001: 65636801 00000074 0000003d 00000020    ech....t...=...
fc0c0011: 0000005f 00000000 00000074 00000061    ..._.......t...a
fc0c0021: 00000000 00000064 00000065 00000035    .......d...e...5
fc0c0031: 00000000 00000062 0000003d 0000006f    .......b...=...o
=> md.w fc0c0001 10
fc0c0001: 0000 3701 0000 6f74 0000 643d 0000 6e20    ..7...ot..d=..n
fc0c0011: 0000 745f 0000 7300 0000 6f74 0000 6c61    ..t_..s...ot..la

This commit implements a workaround at least for the most blatant
problem: using memcpy() from NOR flash. We rename the assembler
routine into __memcpy() and provide a wrapper, which will use a
byte-wise copy loop for unaligned source or target addresses when
reading from NOR flash, and branch to the optimized __memcpy()
in all other cases, thus minimizing the performance impact.

Tested on lite5200b and TQM5200S.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
2010-06-23 02:09:20 +02:00
Anatolij Gustschin
1054382007 video: cfb_console: add weak default video_set_lut()
Do not enforce drivers to provide empty video_set_lut()
if they do not implement indexed color (8 bpp) frame
buffer support. Add default function to the cfb_console
driver and remove empty video_set_lut() functions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-06-14 12:28:28 +02:00
Timur Tabi
6e37a04407 fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-30 11:10:32 -05:00
Wolfgang Denk
45b728cdee Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-26 22:36:32 +02:00
Kumar Gala
6ece2550d1 Convert Makefiles from COBJS-${} to COBJS-$()
Match style we use almost everywhere else

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-26 22:27:38 +02:00
Michael Weiss
59dde44acb powerpc/bootcount: Fix endianness problem
For CONFIG_SYS_BOOTCOUNT_SINGLEWORD the code had an endianness problem.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
2010-05-26 22:26:32 +02:00
Kim Phillips
71bd860cce mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init.c
commit c7190f028f "mpc83xx:
retain POR values of non-configured ACR, SPCR, SCCR, and LCRR
bitfields" incorrectly shifted <register>_<bitfield> (e.g.
ACR_PIPE_DEP) values that were preshifted by their
definition in mpc83xx.h.

this patch removes the unnecessary shifting for the newly
utilized mask values in cpu_init.c, and prevents seemingly
unrelated symptoms such as an mpc8379erdb board from
locking up whilst performing a networking operation,
e.g. a tftp.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:39 -05:00
Horst Kronstorfer
f6970d0c54 Fixed two typos in arch/powerpc/cpu/mpc83xx/start.S.
Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-21 15:22:36 -05:00
Wolfgang Denk
568278e336 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-17 23:16:08 +02:00
Kim Phillips
a4bfc4cc46 mpc83xx: fix NAND bootstrap too big error
commit 167cdad137 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.

this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31 "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-17 14:44:25 -05:00
York Sun
bcb6c2bb84 Enabled support for Rev 1.3 SPD for DDR2 DIMMs
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3.
The difference has ben examined and the code is compatible.
Speed bins is not verified on hardware for CL7 at this moment.

This patch also enables SPD Rev 1.x where x is up to "F". According to SPD
spec, the lower nibble is optionally used to determine which additinal bytes
or attribute bits have been defined. Software can safely use defaults. However,
the upper nibble should always be checked.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:54:30 -05:00
Kumar Gala
f54fe87ace 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabled
On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.

Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
54648985e2 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code.  Use it instead as we convert away from the
is_fsl_pci_cfg() code.

Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:51 -05:00
Kumar Gala
6ab4011b79 85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured.  This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-05-12 04:53:50 -05:00
Wolfgang Denk
ab92d0fd9a Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-05-09 01:16:51 +02:00
Ron Madrid
3b439792b0 mpc83xx: Add UPMA configuration to SIMPC8313
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-05-07 12:19:52 -05:00
Stefan Roese
e4a95d112e powerpc: Consolidate bootcount_{store|load} for PowerPC
This patch consolidates bootcount_{store|load} for PowerPC by
implementing a common version in arch/powerpc/lib/bootcount.c. This
code is now used by all PowerPC variants that currently have these
functions implemented.

The functions now use the proper IO-accessor functions to read/write the
values.

This code also supports two different bootcount versions:

a) Use 2 separate words (2 * 32bit) to store the bootcounter
b) Use only 1 word (2 * 16bit) to store the bootcounter

Version b) was already used by MPC5xxx.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
          for 83xx parts
Cc: Michael Zaidman <michael.zaidman@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-05-06 23:28:48 +02:00
Norbert van Bolhuis
3882d7a5a5 ppc: unused memory region too close to current stack pointer
This avoids a possible overwrite of the (end of) ramdisk by u-boot.
The unused memory region for ppc boot currently starts 1k below the
do_bootm->bootm_start->arch_lmb_reserve stack ptr. This isn't enough since
do_bootm->do_bootm_linux->boot_relocate_fdt calls printf which may
very well use more than 1k stack space.

Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl>
2010-05-05 23:55:02 +02:00
Detlev Zundel
6f5f89f011 Remove unused "local_crc32" function.
For code archeologists, this is a nice example of copy and paste history.

Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-05-03 14:52:48 -07:00
Wolfgang Denk
d03f4230a6 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2010-04-28 00:09:53 +02:00
Wolfgang Denk
8e98f5f70b Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2010-04-27 23:02:12 +02:00
Wolfgang Denk
c303176aa0 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2010-04-27 22:57:41 +02:00
Kumar Gala
7e1afb62a7 ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-26 22:37:57 -05:00
Lan Chunhe
3f0202ed13 mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Dave Liu
0c955dafab 85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:56 -05:00
Kumar Gala
9ce3c22827 85xx: Fix compile warning
cpu.c: In function 'checkcpu':
cpu.c:47: warning: unused variable 'gur'

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Kumar Gala
4db9708b94 85xx: Convert cpu_init_f code to use out_be32 for LBC registers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:55 -05:00
Dave Liu
99bac479dd fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Dave Liu
f8d05e5e58 fsl-ddr: add the macro for Rtt_Nom definition
add the macro definition for Rtt_Nom termination value for DDR3

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:53 -05:00
Kumar Gala
1231c498e0 ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines
Added some needed fines and some misc additional defines
used by p4080 initialization.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Dave Liu
17d90f31a8 ppc/p4080: Extend the GUTS memory map
Extend pin control and clock control to GUTS memory map

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:52 -05:00
Srikanth Srinivasan
ab48ca1a66 ppc/p4080: Fix synchronous frequency calculations
When DDR is in synchronous mode, the existing code assigns sysclk
frequency to DDR frequency.  It should be synchronous with the platform
frequency.  CPU frequency is based on platform frequency in synchronous
mode.

Also fix:

* Fixes the bit mask for DDR_SYNC (RCWSR5[184])
* Corrects the detection of synchronous mode.

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:51 -05:00
Anatolij Gustschin
2ebdb9a9d7 mpc5121: add common post_word_load/store code
Add common post_word_load/post_word_store routines
for all mpc5121 boards. pdm360ng board POST support
added by subsequent patch needs them.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:39 +02:00
Anatolij Gustschin
a3921eefa1 mpc5121: add support for PDM360NG board
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:37 +02:00
Anatolij Gustschin
b9947bbb08 mpc5121: determine RAM size using get_ram_size()
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:35 +02:00
Anatolij Gustschin
5d937e8b59 mpc512x: make MEM IO Control configuration a board config option
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:34 +02:00
Anatolij Gustschin
8e234e33bf mpc5121: add PSC serial communication routines
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:32 +02:00
Anatolij Gustschin
e3b28e6732 mpc512x: add multi serial PSC support
Extend mpc512x serial driver to support multiple PSC ports.

Subsequent patches for PDM360NG board support make use of this
functionality by defining CONFIG_SERIAL_MULTI in the board config
file. Additionally the used PSC devices are specified by defining
e.g. CONFIG_SYS_PSC1, CONFIG_SYS_PSC4 and CONFIG_SYS_PSC6.

Support for PSC devices other than 1, 3, 4 and 6 is not added
by this patch because these aren't used currently. In the future
it can be easily added using DECLARE_PSC_SERIAL_FUNCTIONS(N) and
INIT_PSC_SERIAL_STRUCTURE(N) macros in cpu/mpc512x/serial.c.
Additionally you have to add code for registering added
devices in serial_initialize() in common/serial.c.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 22:56:30 +02:00
Anatolij Gustschin
fbb0030e38 serial: struct serial_device: add uninit() entry for drivers
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.

This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2010-04-24 21:34:07 +02:00
Wolfgang Denk
a77034a8df Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2010-04-24 21:16:57 +02:00
Kim Phillips
1a2e203b31 mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:44:56 -05:00
Kim Phillips
dfe812c744 mpc83xx: use "A" nomenclature only on mpc834x and mpc836x families
marketing didn't extend their postpend-with-an-A naming strategy
on rev.2's and higher beyond the first two 83xx families.  This
patch stops us from misreporting we're running e.g., on an MPC8313EA,
when such a name doesn't exist.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:49 -05:00
Rini van Zetten
27ef578df7 mpc83xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define
instead of a platform define. This will enable all the 83xx
platforms to use sdhc_clk based on CONFIG_FSL_ESDHC.  It's
the same patch as commit 6b9ea08c50
for the ppc/85xx.

Signed-off-by: Rini <rini@arvoo.nl>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-22 18:34:22 -05:00
Stefan Roese
a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00