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14449 commits

Author SHA1 Message Date
Vignesh R
61059bc55a mtd: spi: spi-nor-core: Add 4 Byte addressing support
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
492e65b29b mtd: spi: spi-nor-core: Add SPI MEM support
Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
7aeedac015 mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
6430eea639 spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
76094485e4 spi: spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
12563f768e spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
6d373e523f spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Tom Rini
bdac5e18a8 Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
	pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05 12:29:59 -05:00
Stefan Roese
6d9a98c583 video: Armada XP: Move driver to DM_VIDEO
This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this
move, the legacy interface board_video_init() is removed from the
theadorable board code (only user of this video driver). The support
via DT will be added in a separate patch.

This patch also enables DM_VIDEO for the theadorable board, as this is
needed to not break git bisect'ability.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05 14:23:21 +01:00
Stefan Roese
94f453ea38 pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05 14:22:38 +01:00
Stefan Roese
b52142004f pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-05 14:22:24 +01:00
Tom Rini
e5fd39c886 u-boot-rockchip changes for 2019.04-rc1:
* support for Chromebook Bob
   * full pinctrl driver using DTS properties
   * documentation improvements
   * I2S support for some Rockchip SoCs
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcVG0IAAoJECaAFcEOcohNKVAIAJd3DN/qudcVQdkuvAGK6WIk
 Umxkm6rxHwur7oU+wxvK1p1l/0YTFBeCfo15quH1DkSc/WIUnmBlLmDvqpGVmPmh
 ydZNE9ZChn0OKRIaM6pKJr+3p155cQDe6Mgg2j/5CnNx28KxT+vu7EqZbZvbQPag
 wcZEK6Z6E5jMVHVn2lbLgmsBPmY7ksX168IqpvzTxIj0a4J3n0DcJUnO4RBBS0Q2
 PGEvFhTvigVWs6r6GL0gLn3VwnQX30xQlIuKKORPcdhjk97cJcS4+bRxdTENTKD9
 j3+pgyl1n04O8sPONZS7pH3fvJwtC6SwnoxTYxGrvjedw1LxbyHG3cqcGDg/TJ8=
 =ik3X
 -----END PGP SIGNATURE-----

Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs
2019-02-02 10:11:20 -05:00
Tom Rini
544d5e98f3 - MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
 - MIPS: mt76xx: fix timer frequency
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAlxURx8ACgkQKPlOlyTy
 XBjZWg//eo8rdWidwogApEUcwHqr6jGHrm5RwAaqJpNqLX5sLunNbNtzzNFvNL2o
 quU+8zjnUBgxWnPo/Aasx8cYh7nzW2cahyqsrUXeKjJmGualWMSR93iFmtIBXdmR
 WJg6erbJw6N9LUNA50/SPfSR6DqayvgQnt8kB/GKg5ASpZEfc2o7zzd0HFS3dFY2
 WU4irUY2INbjP3k9Qa+PIm8rOq52z/OqfQ3tX6SuoC1LOaYQJsyrYDmzxmqP4HV2
 JarsOqy1d8II3hsvTKJIypBeyRiln7rtSz0nPyQcUG4VRw9AOtMfnTY93gr0Ruzt
 UMVNnhJr78NzHly7ukqqmFBsQMq+gXbDDq6GbjPEfGcvy7AiprJYjokJ28JwraOi
 yfnwonJQU/k0E5PBX9f4AtkbDOedd/RWPRfQaUmTdGzxoCX/YvrOAe+yqWTov8To
 y5mnhx9QwIC8cxHgjaS7+xAXkcumA4xwG3g7wGntUqMuPmIiJObtZT4umEpLjW4d
 zL5wVmdRIALcTdfHS97T1QpDuJcVjFre98bfRGweXurX/ngQIEbh4e82JojW2CDN
 jAw/tVHkXcKBPoGE/hHEx0K4ScxjdswCXMeqKWjqHotvF+V6Mwnq8frecjgVEUGM
 E/bfSlzAVllfuug7wWccq69pvyQkn7YHg8HDuNwy3gdBCxZFY8c=
 =qCAc
 -----END PGP SIGNATURE-----

Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips

- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency
2019-02-02 10:11:12 -05:00
Adam Ford
3c29a56736 regulator: pbias: Handle extended drain IO when changing omap36 PBIAS
The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS.  This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 14:13:45 -05:00
Philipp Tomsich
5a127325f0 pinctrl: Kconfig: fix missing include of rockchip/Kconfig
After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
efc4677171 pinctrl: Kconfig: sort includes alphabetically
To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
5328af1774 rockchip: clk: Add mention of four new clocks
These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
6831616063 clk: Improve debug message in clk_set_default_rates()
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
David Wu
96f73e0d24 pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
e7ae4cf27a pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
Simon Glass
bcea0e1e81 rockchip: Add a sound driver
Add a sound driver for rk3288 supporting chromebook_jerry. This uses the
I2S driver, and existing audio codec and the clock/pinmux support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
2665f09115 rockchip: Add an I2S driver
Add a driver for I2S which allows audio data to be sent from the SoC to
the audio codec. The sample rate and other settings are hard-coded for now
as there is no suitable device-tree binding available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Jean-Jacques Hiblot
1c1464c2b1 usb: ether: call _usb_eth_halt() if initialization fails
If the host does not respond in time, the initialization fails. However
the usb ether driver will still be registered. This will make
usb_gadget_probe_driver() fail the next time the initialization is
attempted because it cannot find an available UDC.

Fixing this by calling _usb_eth_halt() when the init fails.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-02-01 09:09:40 -05:00
Horatiu Vultur
c5620aeea4 net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is
present on Luton SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
0b8f34dc8c net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private and make
miim variable static.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
45f2748c50 net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
36d04f52ff net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
2fff4a9b59 net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
4c66157f42 net: mscc: Move ocelot_switch to mscc_eswitch folder
Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Tom Rini
db4a29993d - ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
   pulse width (support some quirky displays)
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXFLpkQ4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXLiRAJ9F4WRPFtzn/S77OinRZl2e5isCJACaA/t8hmx2
 M81piE8xdryxVKIHFJc=
 =ocAC
 -----END PGP SIGNATURE-----

Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-video

- ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
  pulse width (support some quirky displays)
2019-01-31 16:07:37 -05:00
Neil Armstrong
3bed422094 video: Add Meson Video Processing Unit Driver
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).

When using HDMI, only DMT modes are supported.

There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
56dd8d87e5 video: dw_hdmi: add support for color conversion
Some IPs like the meson VPU can only feed a particular pixel format to
dw_hdmi. As of now, the driver is hardcoded to use RGB888 as input.

This commit enables different pixel format inputs, with the appropriate
CSC configuration.

Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
fd99841808 video: dw_hdmi: support SoC specific read/write ops
Some IPs like the meson VPU have a specific way to write to dw_hdmi
registers. Make it configurable.

Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
[added commit description]
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
335d287327 power: domain: meson-gx-pwrc-vpu: add missing depends
MESON_GX_VPU_POWER_DOMAIN should depend on POWER_DOMAIN.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Simon Goldschmidt
1f92c074cb dfu: mmc: call fs functions instead of run_command
This unbreaks dfu mmc_file_op which is currently broken since using the
load cmd on a buffer from heap is not allowed - added with
commit aa3c609e2b ("fs: prevent overwriting reserved memory")

Fixes: commit aa3c609e2b ("fs: prevent overwriting reserved memory")
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-30 21:22:53 -05:00
Tom Rini
552452f80c Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Enable DM_MMC support
2019-01-30 12:24:32 -05:00
Andre Przywara
13b0867dc3 sunxi: clk: enable clk and reset for CCU devices
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.

Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-30 18:21:35 +05:30
Tom Rini
748ad078ee For 2019.04
-----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlxQnKQPHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3Mm8L/0P99AB62Pu0NbAaVI9PnqaeR9/kUIvHlaPT
 RMuUIz931/1GDnugGsEEquSMUt69lfBCKYbF4sKiWObytHfYKvB/u638gqG2IoEt
 KcnWU5dagaTOyoyPOtr8EyKxThJtG2j1uN+fA5BCZ6A6CLnEW0biJXYLwN5P/DIE
 bsn9R+XfOV/ppaFh3p65SZfzzwKh6eUQLHqEphBbbAHCPz74QSeZMHkumbKplGOk
 1cjuFi8bekFnPGDDPW8jRvUNlhRD0kTjXoBj1eF2Q1g8lUj6La8yOsq1DAeGJjd1
 ywUDi8GPNYQ7HuHNzfZETWAYspNflARnPQwMemmNSKmmu6CO8aB6lt3JZWEUrnjL
 1D8LzMrRpyq1jEA0a57qsvTc8i3KA7X3FHTszP0flhiLKgBgE+5t1w8dc0wxC7HZ
 eF9TE3tGAmVzRVZwBh8HIDuKhe+y3uGKtvxl80DF8vQQWrXHq0GSC+pmdEXk7DGU
 OGYvdvVoThglZwM4vqeKlT/+1KLPCQ==
 =dOOt
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04
2019-01-30 07:22:12 -05:00
Andre Przywara
4233698dd3 mmc: sunxi: Honour non-removable property in DT
If a board DT describes a cd-gpios property, but also marks the storage
as non-removable, we must ignore the GPIO (as Linux does).

Teach the DM_MMC part of the Allwinner MMC driver about the
non-removable DT property, to fix DM_MMC access on the SoPine and
Pine64-LTS board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:49:41 +05:30
Andre Przywara
c57572eb5a mmc: sunxi: Add DM clk and reset support
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:44:03 +05:30
Jagan Teki
3c8c7da6fc mmc: sunxi: Add DM_MMC support for A80
A80 gates clock already be part of CLK framework, so just
add mod_clk offset with A80 compatible string.

Cc: Rask Ingemann Lambertsen <rask@formelder.dk>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:41:57 +05:30
Jagan Teki
9e23338268 mmc: sunxi: Add DM_MMC support for H6
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:35:18 +05:30
Jagan Teki
a1925a64d5 mmc: sunxi: Add remaining compatible strings
Add MMC compatible strings for A83T, A64, H5.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:34:58 +05:30
Andre Przywara
e0c7ce7e52 sunxi: clk: A80: add MMC clock support
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:33:08 +05:30
Andre Przywara
bb3e5aa289 sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:30:11 +05:30
Jerome Brunet
c4c726c26b pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.

We need to set pinconf provided in DT to solve this

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
2019-01-29 11:19:15 +01:00
Mario Six
6df07d854b ihs_video_out: Fix error handling
The ihs_video_out driver's error handling is incorrect in two places
(one is a missing negation, and in one place a error should be ignored).

Fix these two instances.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-28 21:29:25 +01:00
Priit Laes
0307d95d52 videomodes: Relax EDID validation checks for hsync/vsync pulse width
Current EDID detailed timing parser errors out when either
horizontal or vertical pulse sync width is 0, thus not
allowing a display with EDID listed below work properly.

EDID below works ok within Linux although it warns about
these two fields being 0. Therefore relax the checks a bit
so we can actually use this the screen out of the box.

Of-course, this display itself is somewhat quirky display with
following anti-features:
- HPD pin is not usable
- although resolution is 640x480, only top 240 pixels are visible

$ xxd -p display.edid
00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748
9a2610474f200000010101010101010101010101010101012a08804520e0
0b1020004000953600000018000000fd0034441a2403000a202020202020
0000001000310a20202020202020202020200000001000002a4030701300
782d1100001e006b

$ edid-decode display.edid
EDID version: 1.3
Manufacturer: AMA Model 3e0 Serial Number 1
Digital display
Maximum image size: 15 cm x 5 cm
Gamma: 2.20
RGB color display
First detailed timing is preferred timing
Display x,y Chromaticity:
  Red:   0.6250, 0.3398
  Green: 0.2841, 0.6044
  Blue:  0.1494, 0.0644
  White: 0.2802, 0.3105
Established timings supported:
  640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz
Standard timings supported:
Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm
                640  672  672  709 hborder 0
                480  484  484  491 vborder 0
               -hsync -vsync
               VertFreq: 60 Hz, HorFreq: 29478 Hz
Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz
Dummy block
Dummy block
Checksum: 0x6b (valid)

Signed-off-by: Priit Laes <priit.laes@paf.com>
Signed-off-by: Priit Laes <plaes@plaes.org>
2019-01-28 21:20:05 +01:00
Patrick Bruenn
791c88da31 mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc
Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28 20:55:46 +01:00
Adam Ford
96d0be07e7 MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT
The initialization function calls a nand_chip.scan_bbt(mtd) but
scan_bbt is never initialized resulting in an undefined function
pointer.  This will direct the function pointer to nand_default_bbt
defined in the same file.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:55:46 +01:00
Ye Li
65a106e36f spi: mxc_spi: Fix build warning on ARM64 platforms
When building mxc_spi driver on ARM64 platforms, get below build warnings.
Fix it in this patch.

In file included from include/common.h:48:0,
 from drivers/spi/mxc_spi.c:9:
 drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’:
drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~
 drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Ye Li
11a1c27eb4 pinctrl: imx: Fix select input issue
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.

    if (input_val >> 24 == 0xff)

Fix the issue by changing the input_val, config_val and mux_mode to u32.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
1610368234 gpio: introduce CONFIG_SPL_DM_PCA953X
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
04b249656e imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Martyn Welch
774ec60b74 Enable FEC driver to retrieve PHY address from device tree
Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 12:47:15 +01:00
Tom Rini
0da9025508 Merge branch '2019-01-25-master-imports'
- snapdragon 820c improvements
- poplar updates
- DFU + SPL cleanups
- Improve the mediatek mmc driver
- Other minor cleanups / improvements
2019-01-26 22:47:55 -05:00
Michal Simek
e38cef9f6e misc: i2c_eeprom: Add atmel,24c08 to the list
Linux kernel binding is using atmel,24c08 compatible string. On the
other hand there is atmel,24c08a which is not listed in the kernel.
Add compatible string without "a" suffix to be compatible with Linux
kernel binding.

These eeproms are available on several ZynqMP development boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-26 08:13:57 -05:00
Angelo Dureghello
1f15cb8f5b drivers: esdhc: add support for ColdFire mcf5441x family
This patch has been tested on the mcf54415-based stmark2
board. The eSDHC driver works reliably using DMA mode.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2019-01-26 08:13:56 -05:00
Andrew F. Davis
2d59ec8482 dfu: Make DFU support more SPL friendly
Do this by using $(SPL_) in Makefiles and CONFIG_IS_ENABLED in C code.
This ensures the files and features are only built into the right build
for which they are enabled. Using the macros to simplify this patch was
made possible by the config symbol rename done in the last patch.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26 08:13:55 -05:00
Andrew F. Davis
6536ca4d66 spl: Kconfig: Drop the _SUPPORT postfix from SPL_DFU
The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same
meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT
to allow for cleaner use in code.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-26 08:13:54 -05:00
Fabien Parent
70dbbd7269 mmc: mtk-sd: fix SPL compilation when GPIO=y and SPL_GPIO=n
It is not possible to link the SPL image when CONFIG_GPIO is enabled
but CONFIG_SPL_GPIO is not.  Use the IS_ENABLED macro instead to
correctly check whether CONFIG_{SPL_}GPIO is enabled.

This commit fixes the following errors:
	* undefined reference to `dm_gpio_get_value
	* undefined reference to `gpio_request_by_name'

Signed-off-by: Fabien Parent <fparent@baylibre.com>
[trini: Move guard to fix warning in msdc_ops_get_wp()]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-26 08:13:54 -05:00
Fabien Parent
924ed344a7 mmc: mtk-sd: fix possible incomplete read ops
The code is checking for incomplete read when it see the INT_XFER_COMPL
flag, but it forget to first check whether there is anything left in the
FIFO to copy to the RX buffer. This means that sometimes we will get
errors because of erroneous incomplete read operation.

This commit fixes the driver re-ordering the code so that we first
check for data inside the RX fifo and only after check the status
of the INT_XFER_COMPL flag.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-01-26 08:13:54 -05:00
Shawn Guo
94f139a9ce mmc: hi6220_dw_mmc: add compatible for Poplar support
It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC
Hi3798CV200 to probe this mmc driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-01-25 12:12:57 -05:00
Tom Rini
87f78478a4 Merge tag 'arc-fixes-for-2019.04-rc1' of git://git.denx.de/u-boot-arc
A couple of trivial fixes and improvements for ARC

Most notable are:
 * Move of ENV_SIZE/ENV_OFFSET to Kconfig
 * Fix with private structure allocation for arc_uart
 * Definition of CONFIG_SYS_CACHELINE_SIZE useful for building drivers
2019-01-25 10:41:24 -05:00
Alexey Brodkin
d771dd531a serial_arc: Allocate buffer for private data
Apparently we never allocated buffer for arc_serial_platdata
which for some reason never caused problems when executed in nSIM.
But in Qemu this causes expected problems.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-01-25 08:40:26 +03:00
Tom Rini
d01806a8fc Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-01-24 15:30:48 -05:00
Tom Rini
68489ed037 Merge branch 'master' of git://git.denx.de/u-boot-net 2019-01-24 15:30:06 -05:00
Valentin-catalin Neacsu
91c9cbabf9 net: phy: aquantia: Print information on config
Print information about Aquantia system interface and firmware loaded
on the phy.

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Valentin-catalin Neacsu
c54bfbf96f net: phy: aquantia: Enable autoneg when on USXGMII
If System Interface protocol is USXGMII then enable USXGMII autoneg

Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
67bb984249 net: remove CONFIG_MCAST_TFTP
No mainline board enables CONFIG_MCAST_TFTP and there have been
compilation issues with the code for some time. Additionally, it has a
potential buffer underrun issue (reported as a side note in
CVE-2018-18439).

Remove the multicast TFTP code but keep the driver API for the future
addition of IPv6.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:30 -06:00
Chris Packham
1a4af5c562 net: move ether_crc to tsec driver
ether_crc was added to the core net code in commit 53a5c424bf
("multicast tftp: RFC2090") so that other drivers could use it. However
the only current user of it is tsec.c so move it there.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Carlo Caione
e57c9fdb04 net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:

1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
   Standard Registers)

Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Ramon Fried
9043c4e0fc net: macb: fix mapping of registers
Some architectures (MIPS) needs mapping to access IOMEM.
Fix that.

Fixes: f1dcc19b21 ("net: macb: Convert to driver model")

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Aditya Prayoga
18bfc8fa84 net: mvneta: Add GPIO configuration support
This patch add GPIO configuration support in mvneta driver.
Driver will handle PHY reset. GPIO pins should be set in device tree.

Ported from mvpp2x
[https://patchwork.ozlabs.org/patch/799654/]

Initial discussion to port the changes into mvneta
[https://patchwork.ozlabs.org/patch/1005765/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Tested-by: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Chris Packham
92f129f4a0 net: mvgbe: fallback phy-mode to GMII
Some existing device trees don't specify a phy-mode so fallback to GMII
when a phy-mode is not provided.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:29 -06:00
Andreas Pretzsch
3b4cda34d4 net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
21586cdd50 net: mvpp2: mdio device per port
Current code forces all ports on a given Ethernet device to use the same
mdio device. In practice different ports might be wired to separate mdio
devices. Move the mdio device from the container struct mvpp2 to the per
port struct mvpp2_port.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:28 -06:00
Baruch Siach
acce753dfb net: mvpp2: fix lookup of mdio registers base address
Current mdio base lookup code relies on a 'reg' property at the upper CP
node. There is no 'reg' property there in current DT files of Armada
CP110. Use ofnode_get_addr() instead since it provides proper DT address
translation.

Cc: Ken Ma <make@marvell.com>
Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
7efb75b114 net: designware: clear padding bytes
Short frames are padded to the minimum allowed size of 60 bytes.
However, the designware driver sends old data in these padding bytes.
It is common practice to zero out these padding bytes ro prevent
leaking memory contents to other hosts.

Fix the padding code to zero out the padded bytes at the end.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:27 -06:00
Simon Goldschmidt
ae8ac8d423 net: designware: fix tx packet length
The designware driver has a bug in setting the tx length into the dma
descriptor: it always or's the length into the descriptor without
zeroing out the length mask before.

This results in occasional packets being transmitted with a length
greater than they should be (trailer). Due to the nature of Ethernet
allowing such a trailer, most packets seem to be parsed fine by remote
hosts, which is probably why this hasn't been noticed.

Fix this by correctly clearing the size mask before setting the new
length.

Tested on socfpga gen5.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24 11:35:27 -06:00
Pankaj Bansal
b3eabd82f2 net: phy: Add clause 45 identifier to phy_device
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 11:35:26 -06:00
Michal Simek
84de0f9188 i2c: cdns: Convert to livetree function
Update cadence i2c driver to support livetree
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:45 +01:00
Luca Ceresoli
8df324a20b fpga: zynqmp: show an error message when FPGA programming fails
When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.

Print the error message unconditionally so the error doesn't go
unnoticed.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:43 +01:00
Siva Durga Prasad Paladugu
c256d3f7c5 net: phy: Move fixed link code to separate routine
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24 10:03:43 +01:00
Stefan Theil
1059858061 zynq-gem: Use appropriate cache flush/invalidate for RX and TX
The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.

Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Michal Simek
25aed77f51 mmc: zynq: Remove unused pwrseq variable
This variable was incorrectly added by:
"mmc: zynq_sdhci: Add support for SD3.0"
(sha1: d1f4e39d58)
which had nothing to do with MMC power sequence provider.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
T Karthik Reddy
97fca6a146 mtd: nand: arasan_nfc: Add support for nand multi chip select
This patch adds support for nand multi chip select.
Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number
of nand chips.

Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Horatiu Vultur
5c31ce36e3 pinctrl: mscc: Add gpio and pinctrl for Serval SoC family.
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:28:09 +01:00
Horatiu Vultur
177c07f829 pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-23 18:27:26 +01:00
Gregory CLEMENT
c8546163fa net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-23 18:26:44 +01:00
Tom Rini
e8ddbefccd Merge git://git.denx.de/u-boot-marvell
- Sync Armada-38x dts with Linux 4.20 from Chris
- Misc changes and enhancements to Turris Mox (v4) from Marek
- Reserve PSCI area for Armada 8k from Heinrich
- New Allied Telesis x530 board (Armada-385) from Chris
- Misc minor changes (defconfig etc)
2019-01-21 11:59:21 -05:00
Derald D. Woods
49ad40298c ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-21 08:36:11 -05:00
Marek Behún
7b03e9969c watchdog: armada_37xx: Fix compliance with kernel's driver
The Armada 37xx watchdog driver was recently accepted for mainline
kernel by watchdog subsystem maintainer, but the driver works a little
different than the one in U-Boot. This patch fixes this.

In the previous implementation there was a tiny period of time when the
watchdog was disabled and the system was vulnerables - this was during
pinging, which was done by disabling, setting, and enabling the counter.

Now pinging is done without disabling the watchdog. We use 2 counters:
Counter 1 is the watchdog counter - on expiry, the system is reset.
Counter 0 is used to reset Counter 1 to start counting from the set
timeout again. So Counter 1 is set to be reset on Counter 0 expiry event
event and pinging is done by forcing an immediate expiry event on
Counter 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-01-21 11:39:49 +01:00
Philipp Tomsich
2acc24fc28 Kconfig: Migrate BOUNCE_BUFFER
The bounce buffer is used by a few drivers (most of the MMC drivers)
to overcome limitations in their respective DMA implementation.

This moves the configuration to Kconfig and makes it user-selectable
(even though it will be a required feature to make those drivers
work): the expected usage is for drivers depending on this to 'select'
it unconditionally from their respective Kconfig (see follow-up
patches).

This commit includes a full migration using moveconfig.py to ensure
that each commit compiles.  To ensure bisectability we update
dependencies of various drivers to now select BOUNCE_BUFFER when needed.

[trini: Squash all patches to ensure bisectability]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> [dw_mmc portion]
Reviewed-by: Fabio Estevam <festevam@gmail.com> [mxsmmc portion]
Reviewed-by: Simon Glass <sjg@chromium.org> [tegra portion]
2019-01-19 09:49:26 -05:00
Tom Rini
77c07e7ed3 Add TFA boot flow for more boards
Add TFA boot defconfig for ls1088a and ls2088a.
 Add dts fixup for PCIe endpoint and root complex.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlxCFVMACgkQ7UVZlNoL
 nbQJaA/9GQ+FpUj8AzsWmLd1JYMdjQeoltlYSicqV1oPkzjX3BsPncAYsr6cW2rm
 SMkriCw+xrlTgC8ge1dyzKxWqMovGzUFEGxpDJqIKCc16s8A/Ro+R0y8saNq1Y89
 MI2axPoaPDT4ZRCSWMzzFVv3lfdvFgGyygZljNlmiKqWp1//fE0OJD4ggE8SqgVo
 +5cMmufuhQhuFuFulQw6YwAOdrJ0eN8wb1SB9wJ8zwdwKn6Oy4CgkRGjJEjKRNoK
 Posw8FUPxQybXmsXW2vie9oomQqmI2A1ILzl1KvdRHSbW0N6P7MbAgsGH1vDPW0u
 dDAsutmkjYR7Ihq/4/5jcTdjkPd7LRJU/SSJzRSnZSD1uLDt5Z4jerQBq0BN9nMR
 peUS/nQ5LTT+rGBRevFT1I0hGNVHhArKGpumV8VRxlq7a30lUPSKhd3jOsadqVLU
 TchCZPjFIVaTrlz9NoX0Wa8bz+m5v1MygRiPkxERc8ft3cudn3rI83neeK1WVKSy
 uwSttQ+Q2uPXBvPq80fIKNToxkEBihPCbEHXZUUs3iE3r+jnRLAZ8CelAn1qK7n6
 fw1oduqOqupPVtYaLHZa6fAWj7lX0FCSge7z4oYu4ezCtoCutzUb6rgwHCpSLEA0
 OF/3fzb+Gn68GpcP23P0pPx+0UplEcmOT+f2/fUXgarUyxd5H/Y=
 =vNy2
 -----END PGP SIGNATURE-----

Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.
2019-01-18 23:11:51 -05:00
Jagan Teki
543049ab59 usb: host: Drop [e-o]hci-sunxi drivers
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
29d280c88a sunxi: usb: Switch to Generic host controllers
Onc of key blocker for using USB Generic host controller
drivers in Allwinner are CLK and RESET drivers, now these
available for USB usage.

So switch sunxi USB use EHCI and OHCI Generic controllers.

Enabling USB is wisely a board choise, So Enable USB_OHCI_HCD
where it already have USB_EHCI_HCD

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
b9aa0a9332 musb-new: sunxi: Use CLK and RESET support
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18 22:19:09 +05:30
Jagan Teki
089ffd0aed phy: sun4i-usb: Use CLK and RESET support
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-18 22:19:09 +05:30
Jagan Teki
6901aab8e3 clk: sunxi: Add Allwinner A80 CLK driver
Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
337fcdc06b clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for
  H6, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
8606f960d4 clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4acc711930 clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
6239a6d092 clk: sunxi: Add Allwinner V3S CLK driver
Add initial clock driver for Allwinner V3S.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for V3S, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for V3S, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
78eb2a41f3 clk: sunxi: Add Allwinner R40 CLK driver
Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_gate
  for R40, so it can accessed in common clk enable
  and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for R40, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
03d87f5909 clk: sunxi: Add Allwinner A83T CLK driver
Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A83T, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A83T, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
3ab029368a clk: sunxi: Add Allwinner A23/A33 CLK driver
Add initial clock driver for Allwinner A23/A33.

- Implement USB bus and USB clocks via ccu_clk_gate table
  for A23/A33, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
  for A23/A33, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
4927e2e8d3 clk: sunxi: Add Allwinner A31 CLK driver
Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table
  for A31, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
  for A31, so it can accessed in common reset deassert
  and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:09 +05:30
Jagan Teki
c8e743c1e8 clk: sunxi: Add Allwinner A10s/A13 CLK driver
Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10s/A13, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
6590bd8c47 clk: sunxi: Add Allwinner A10/A20 CLK driver
Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table
  for A10/A20, so it can accessed in common clk enable and
  disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
e945816efb clk: sunxi: Add Allwinner H3/H5 CLK driver
Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for
  H3/H5, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
  H3/H5, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
99ba430870 reset: Add Allwinner RESET driver
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Jagan Teki
0d47bc7056 clk: Add Allwinner A64 CLK driver
Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:19:08 +05:30
Chris Packham
8e34c1d34a video: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-18 09:16:15 -05:00
Chris Packham
cb4d1bbe51 pinctrl: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Chris Packham
7475145449 i2c: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-01-18 09:16:15 -05:00
Chris Packham
83e7a4d597 drivers: Kconfig: spelling fixes
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-18 09:16:15 -05:00
Tom Rini
f83ef0dac8 - MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
 - MIPS: optimised SPL linker script
 - MIPS: bcm6368: fix restart flow issues
 - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
 - MIPS: mt7688: small fixes and enhancements
 - mmc: compile-out write support if disabled
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAlw/LR0ACgkQKPlOlyTy
 XBg46xAAv3/7/aZuBhTYLmPuApcjJ/STGwHKtJTZUQtij6pxqbYDQB2AVzmjEbwk
 JR9KfXgvqcJK/XU3qVmrIs4kiHIKpC+y2diBgiCY26UVRFrmeKxP6T/AqLH6wCCG
 PEv0cE3U+XX2RX8VN0cItdhOuwnkbg09ToxAqfBrfPDTvI4xEO1EB28IVYozD16B
 ucBdUFkG4hB5JFqc+Sx8pJ2iSq4SmOp+mHD4sHM2XpbuMB4UnRNkjzQPk7gLHZUo
 i8wQ6tJoDKY07u9//QE75BkND/5dm1PflCNIrvH1/aJlv32lbHHf8Mm/ZEKCcth0
 dFAhalFnhl8TF8l8MgmDmjtlE52u9GUVGBJpRfc7EX1EzLm2dVu62dxBl9r4qyXM
 jj5BZBoXFeaeuA3Zm8Oui+jbkKExiuJOAgbvb5vMzyaQYN0mQjFyMBCOQQzBqBoe
 sRh/itYb0Ie0F0B2Y96mx1UgTQ4LGWtBaWrnuCQhrIB9iwt1vHA6DWNfA5PMelDK
 6iHLVBKYsV6sU+f7Ua9krczwP1p6y9u5XzW9teM7BLO5ab2vsI5/wz78OutAKmul
 NylqF3vtZDSGKz/duvEE54e4ltux0/xv5CFV/xO/bEiScNxGu8OPVIvtaAmgRomG
 vE7m63ZoI5DaxOpuBX4Qh8xOomshu3fM+1LnZ6sjulMXpoAE1vc=
 =Mxqj
 -----END PGP SIGNATURE-----

Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips

- MIPS: mscc: various enhancements for Luton and Ocelot platforms
- MIPS: mscc: added support for Jaguar2 platform
- MIPS: optimised SPL linker script
- MIPS: bcm6368: fix restart flow issues
- MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards
- MIPS: mt7688: small fixes and enhancements
- mmc: compile-out write support if disabled
2019-01-17 19:12:55 -05:00
Xiaowei Bao
59a557f360 pci: layerscape: Add the dts fixup for EP and RC
Add the dts fixup when PCI controller work diffferent mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:40 -08:00
Xiaowei Bao
87e0d2b9ac pci: layerscape: Do not scan when PEX work in EP mode
Don't scan the bus when the PEX work in EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:33 -08:00
Xiaowei Bao
5bd3c9d556 pci: layerscape: Modify the EP and RC mode judge method
Modify the RC and EP mode judge method, save the mode as a variable,
the variable will be used by other function.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:28 -08:00
Yinbo Zhu
7a0425dd96 mmc: fsl_esdhc: make get_cd work well in dm_mmc_ops
This patch is to make get_cd work well when DM_MMC enabled

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:17:10 -08:00
Mian Yousaf Kaukab
7e96804975 fsl-layerscape: dpaa: fix fsl-mc status in fdt with bootefi
fsl-mc lazyapply command applies dpl from efi_exit_boot_services().
Status of fsl-mc node in working fdt is updated at this stage.
However, an efi application like grub may already have copied the fdt.
So the updates to fdt done at efi_exit_boot_services() may not be
visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply
command is used.

Fixes: b7b8410a8f (ls2080: Exit dpaa only right before exiting U-Boot)
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:16:49 -08:00
Rajesh Bhagat
bf0f791087 drivers: ifc: restore the legacy flow for IFC config
Restore the legacy flow along with TFABOOT flow for
IFC configuration.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17 13:15:53 -08:00
Stefan Agner
a38c3af868 mtd: nand: raw: allow to disable unneeded ECC layouts
Each ECC layout consumes about 2984 bytes in the .data section. Allow
to disable the default ECC layouts if a driver is known to provide its
own ECC layout.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-16 16:14:45 -05:00
Horatiu Vultur
051de9b3eb pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
ace9c103df mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
fd6e0b0525 mips: spi: mscc: Add fast bitbang SPI driver
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.

Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Ezequiel Garcia
82d5464788 mmc: jz_mmc: Compile-out write support if disabled
Do not build write support, unless it's enabled.

In the SPL case, this change will typically remove
precious bytes (as write support is most often
not needed in SPL).

This is important on this platform, where the maximum
SPL size is 14 KiB.

With gcc v7.3, this change saves 144 bytes producing:

size spl/u-boot-spl
   text	   data	    bss	    dec	    hex	filename
   9240	    752	    712	  10704	   29d0	spl/u-boot-spl

To make the code easier to compile-out and more
readable, a pair of read_data/write_data helpers are created.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Ezequiel Garcia
2a4bb3d271 mmc: Use proper IS_ENABLED macro to check block support
Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK,
in order to fix the following build issues when
CONFIG_SPL_MMC_WRITE is selected:

drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase'
 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
       ^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was here
 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt);
       ^~~~~~~~~~
drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite'
 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
       ^~~~~~~~~~
In file included from drivers/mmc/mmc_write.c:15:0:
drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was here
 ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
       ^~~~~~~~~~

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Álvaro Fernández Rojas
a4ae422570 net: bcm6368: fix restart flow issues
Correctly enable/disable bcm6368-net controller to avoid flow issues.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
be8313feee mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Tom Rini
aac0c29d4b Fix recent changes to serial API for driver model
Buildman clang support and a few fixes
 Small fixes to 'dm tree' and regmap test
 Improve sandbox build compatibility
 A few other minor fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlw+AlIACgkQfxc6PpAI
 reYchAf+L/P5JsLoCKAY84v11eWQkCS44idAYStD8Q023dyuyNC/W6G3qEQVGkHu
 SXBzNrZ5wSJanN5I3h3ktJ7yfMOYIvSO2qLHphxDstPaZbCY4Zac6NywHrHxQpA9
 fbSilQRbcVWrPo5rsjjZhXmMdQRZVOmGD6CYZj1AihWAiHfYth7f6laNWNTWQA8C
 z+aoiF70t/PbvwFbgdzzYOjoGdXI9XML0xTqdLWRlsBKjf3z54pCV6LmN2xrsrDZ
 k7lr+x7ajJUFhivxzjowf4aOjhDB+/+I3sr+hJ5vkMM0Kqg14bbEU+xJRGpDc18K
 QPvVHT5JGe/nq1cZXuCqzrYxTrrA7A==
 =w9ln
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-15jan19' of git://git.denx.de/u-boot-dm

Fix recent changes to serial API for driver model
Buildman clang support and a few fixes
Small fixes to 'dm tree' and regmap test
Improve sandbox build compatibility
A few other minor fixes
2019-01-15 22:05:34 -05:00
Tom Rini
f4cfd73943 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2019-01-15 22:05:28 -05:00
Tien Fong Chee
31a2cf1ca4 misc: fs_loader: Switching private data allocation to DM auto allocation
Switching private data manual allocation to driver model auto allocation
so users no longer need to deallocate themself because this would be
deallocated by driver model when the device is no longer required.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:54 -05:00
Marek Vasut
2e89bbefdc blk: Increase cache element size
Cache up to 4 kiB entries. 4 kiB is the default block size on ext4, yet
the underlying block layer devices usually report support for 512B . In
most cases, the 512B support is emulated (ie. SD cards, SSDs, USB sticks
etc.) and the real block size of those devices is much bigger.

To avoid performance degradation with such devices and FS setup, bump
the maximum cache entry size to 4 kiB.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:53 -05:00
Simon Goldschmidt
c4448bdc4f serial: ns16550: fix debug uart putc called before init
If _debug_uart_putc() is called before _debug_uart_init(), the
ns16550 debug uart driver hangs in a tight loop waiting for the
tx FIFO to get empty.

As this can happen via a printf sneaking in before the port calls
debug_uart_init(), introduce a config option to ignore characters
before the debug uart is initialized.

This is done by reading the baudrate divisor and aborting if is zero.

The Kconfig option is required as reading the baudrate divisor does
not seem to work for all ns16500 compatibles (which is why the last
attempt on this has been reverted in 1a67969a99).

Tested on socfpga_cyclone5_socrates.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Simon Goldschmidt
7828e3cf70 drivers: serial: DEBUG_UART_SKIP_INIT depends on DEBUG_UART
DEBUG_UART_SKIP_INIT is used only by debug UART and thus should depend
on DEBUG_UART.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-15 15:28:52 -05:00
Marek Vasut
b9a2a0e2e9 mmc: Add support for downgrading HS200/HS400 to HS mode
The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.

In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.

However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-01-15 15:28:42 -05:00
Manivannan Sadhasivam
6240e64f92 mmc: Convert HI6220 MMC driver to driver model
Convert HiSilicon HI6220 MMC driver based on DWMMC IP to driver
model.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Enable this on poplar]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-15 15:28:10 -05:00
Michal Simek
1d7b6a5c4f i2c: Reflect correct dependency for !DM cadence driver
Setup proper DM_I2C dependency.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:06:46 +01:00
Michal Simek
58dc4a99b7 i2c: mux: Covert to livetree functions
Updates i2c muxes drivers to support livetree.
Similar changes were done by:
"net: zynq_gem: convert to use livetree"
(sha1: 26026e695a)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:06:28 +01:00
Tomasz Gorochowik
f48ef0d81a i2c: i2c-cdns: Use proper input frequency
This is needed to properly calculate i2c bus speed divisors.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-15 09:04:49 +01:00
Marek Vasut
ad827a500b i2c: xiic: Add Xilinx AXI I2C driver
Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver.
This driver is stripped of all the IRQ handling and uses pure polling,
yet tries to retain most of the structure of the Linux driver to make
backporting of fixes easy.

Note that the IP has a known limitation on 255 bytes read and write,
according to xilinx this is still being worked on [1].

[1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-I2C-Master-Reading-multiple-bytes-from-I2C-slave/m-p/854419/highlight/true#M39387

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-01-15 09:04:49 +01:00
Simon Glass
a61cbad78e dm: serial: Adjust serial_getinfo() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
3de04e771c dm: serial: Adjust serial_setconfig() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
67d1b05130 dm: serial: Adjust serial_getconfig() to use proper API
All driver-model functions should have a device as the first parameter.
Update this function accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-01-14 17:47:13 -07:00
Simon Glass
8405452e6a net: Fix error handling in sb_eth_raw_ofdata_to_platdata()
At present this stores the error number in an unsigned int so an error is
never detected. Use the existing signed variable instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-14 17:47:13 -07:00
Simon Glass
54d2cfe6ee dm: Tidy up 'dm tree' output when there are many devices
At present the 'Index' column assumes there is only one digit. But on some
devices (e.g. snow) there are a lot of regulators and GPIO banks. Adjust
the output to allow for two digits without messing up the display.

Also capatalise the heading to match.

Fixes: 5197dafc42 (dm: core: Widen the dump tree to show more of the
driver's name.)

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Liviu Dudau <liviu.dudau@foss.arm.com>
2019-01-14 17:47:13 -07:00
Weijie Gao
23f17164d9 ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs
This patch adds ethernet support for Mediatek ARM-based SoCs, including
a minimum setup of the integrated switch.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-By: "Frank Wunderlich" <frank-w@public-files.de>
2019-01-14 17:43:18 -05:00
Weijie Gao
2dca3cc2a9 clk: MediaTek: bind ethsys reset controller
The ethsys contains not only the clock gating controller, but also the
reset controller for the whole ethernet subsystem and its components.

This patch adds binding of the reset controller so that the ethernet node
can have references on it.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Weijie Gao
3e066bcaef reset: MedaiTek: add reset controller driver for MediaTek SoCs
This patch adds reset controller driver for MediaTek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-01-14 17:43:18 -05:00
Fabio Estevam
29c2edb42b mmc: fsl_esdhc: Avoid infinite loop in esdhc_send_cmd_common()
The following hang is observed on a Hummingboard 2 MicroSOM
i2eX iMX6D - rev 1.3 with no eMMC populated on board:

U-Boot SPL 2018.11+gf6206f8587 (Nov 16 2018 - 00:56:34 +0000)
Trying to boot from MMC1

U-Boot 2018.11+gf6206f8587 (Nov 16 2018 - 00:56:34 +0000)

CPU:   Freescale i.MX6D rev1.5 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 33C
Reset cause: POR
Board: MX6 HummingBoard2
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
---> hangs

which is caused by the following infinite loop inside esdhc_send_cmd_common()

	while (!(esdhc_read32(&regs->irqstat) & flags))
		;

Instead of looping forever, provide an exit path so that a timeout
error can be propagated in the case irqstat does not report
any interrupts, which may happen when no eMMC is populated on
board.

Reported-by: Ricardo Salveti <rsalveti@rsalveti.net>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Ricardo Salveti <rsalveti@rsalveti.net>
2019-01-14 11:26:12 -05:00
Tom Rini
7f9418688d Merge branch 'master' of git://git.denx.de/u-boot-usb 2019-01-11 10:47:41 -05:00
Lukasz Majewski
b6a6238f04 Revert "dm: pinctrl: Prevent (re-)configuring pins when already done before relocation"
This reverts commit a7f4b4b344.

As reported by Alex Kiernan the above optimization introduces a
regression in the below use case where:

1. Device has defined 'u-boot,dm-spl' property (@ eMMC DTS node)

2. The device downloads its MLO/SPL via UART (not eMMC - the eMMC pinmux
pins are NOT probed/configured in MLO/SPL).

3. The loaded via UART MLO/SPL wants to load Linux from eMMC. In this case
the DM core and pinctrl uclass checks 'u-boot,dm-spl' and don't
configure pins (as it thinks that those were initialized in MLO/SPL).

As we are very close to release - please revert this commit.

Reported-by: Alex Kiernan <alex.kiernan@gmail.com>
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-11 10:03:42 -05:00
Jean-Jacques Hiblot
b3c518a882 dm: usb: gadget: Fix boot breakage on sunxi platforms
Fixes commit 0131162439 ("dm: usb: create a new UCLASS ID for USB gadget
devices")

The UCLASS_DRIVER for id UCLASS_USB_GADGET_GENERIC needs to be declared
even for platforms that do not enable DM_USB_GADGET. Otherwise the driver
for their usb peripheral controller fails to bind.

Reported-by: Priit Laes <plaes@plaes.org>
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Priit Laes <plaes@plaes.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-10 18:53:03 +01:00
Jean-Jacques Hiblot
f811e9763f Kconfig: rename CONFIG_SPL_USB_GADGET_SUPPORT as CONFIG_SPL_USB_GADGET
The SPL option for USB gadget should be named after the option for u-boot
(CONFIG_USB_GADGET)

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-01-10 18:52:55 +01:00
Jean-Jacques Hiblot
801f1fa442 dm: usb: udc: Use SEQ_ALIAS to index the USB gadget ports
dfu, fastbot and other usb gadget commands take the USB port index as a
parameter. Currently this index is assigned in the order of the driver
bindings.
Changing this behavior using the SEQ_ALIAS feature. This option assign to
the device a SEQ number based on its alias (if it exists)

To use it we must set the DM_UC_FLAG_SEQ_ALIAS flag and follow the existing
naming convention: use "usb" for the name of the gadget UCLASS_DRIVER
(same as for the UCLASS_USB).

If no alias is provided, then the index falls back to the order in which
the bindings took place.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-01-10 18:52:51 +01:00
Tom Rini
64abfc9b6b Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2019-01-10 09:28:28 -05:00
Tom Rini
e5aa3f4d97 Fixes for 2019.01
-----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlw2/EgPHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et32w4MAInrLv5lIvzwlcCxsX25cbWO8TSRemt4Stbl
 g01Cq/yaHkTs/VTpHHqtuAy+PHBx6pFSIJNp8zheNy/VGMHavb+RSVH3d+KM6uU3
 qCfVQq3ZMm4NyvbnrJSW6Uu2qmmEJQssldWuRhIIEFK1nCrYKQp9eyo215miLbFE
 9b1MWFO+XV0Qz+HZQsk2ApiuvmaXu3qpvZ0tRRi9xb2dGJYYTuEcfvbehy7Iejta
 +JKd3wtZaKj1JDdsDFQoJs55OAdJySTSYAeNVzlstQ+1fYArB3Ju4et2QInWbXuF
 x/NdFAzyAtl4xOf8yQ9kbALa3TlofhPu9fJm7bniC3hf+ZPPwdS3jlvEy+DeCJIU
 tX/es+WgUVciiCfRHXS1RgFuHGDDpO5qi2RjSLqq6yRhlBAvXYhET2YCU9RLoLHY
 D57V6lkFl7jWto8xS7GoicKvGPS5MwjARw917TSocJzhJz86PeJBhOW6tR+E2/Zh
 kCDDCrKlyuLRg+2/eFV5H91TalwjQQ==
 =vYKZ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imx

Fixes for 2019.01
2019-01-10 09:28:16 -05:00
Jagan Teki
e8f37f4203 mmc: sunxi: Fix mmc clocks for DM_MMC
Existing clock configure code has been followed based on the
legacy MMC dt node definitions and it cannot work with recent
dts(i) sync from Linux.

So, add clock configure code for Allwinner platforms which support
DM_MMC and eventually this will drop once CLK support is in Mainline.

Fixes: 3c92cca3cd ("ARM: dts: sun4i: Update A10 dts(i) files from Linux-v4.18-rc3")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Priit Laes <plaes@plaes.org> # Gemei G9 A10 Tablet
Tested-by: Marek Kraus <gamelasterv2@gmail.com> # A10-OLinuXino-Lime
2019-01-10 14:45:15 +05:30
Peng Fan
026381fc5a misc: imx8: scu: use platdata instead of priv data
priv data has not been allocated when doing bind, so it is
wrong to use dev_get_priv in bind call back.

Let's switch to use platdata in the driver to fix the issue.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-09 17:04:03 +01:00
Peng Fan
ecab65e4cd misc: imx: scu: avoid write null pointer
When boot_dev is true, fill boot device. However the original logic is when
boot_dev is false, fill boot device, this will trigger data abort.

Also fix sc_misc_get_control when using pointer val.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-09 17:03:45 +01:00
Peng Fan
224f745247 clk: imx8: fix build warning
When build clk driver in spl, met the warning:
"
drivers/clk/imx/clk-imx8.c:21:25: warning: ‘imx8_clk_names’ defined but not used [-Wunused-variable]
 static struct imx8_clks imx8_clk_names[] = {
                         ^~~~~~~~~~~~~~
"

Fix with wrapping the array with CONFIG_CMD_CLK.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-09 17:03:29 +01:00
Ye Li
8c6cc71b40 usb: xhci-mem: Fix scratchpad array issue
After updating the value of dev_context_ptrs[0], we should flush this
from cache to memory. Otherwise the xhci controller won't use it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-01-09 16:03:56 +01:00
Patrice Chotard
4fb224638d gpio: stm32f7: Fix SPL code size
In order to keep SPL code size below the 32Kb limit,
put under CONFIG_SPL_BUILD flag all unused code in SPL.
This is needed for stm32f7xx board which are using SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-01-09 07:13:33 -05:00
Patrice Chotard
39a8f0be2d gpio: stm32f7: Fix gpio bank hole management
In case "gpio-ranges" property is not present in device tree,
use default value for gpio_count and gpio_range.
This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a"
command didn't return any pin status due to the fact that both stm32 F7
and H7 board DT doesn't use the gpio-ranges property.

Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-01-09 07:13:32 -05:00
Andre Przywara
eef05fd3ba mmc: bring back partition init for non-DM MMC drivers
Commit d0851c8937 ("blk: Call part_init() in the post_probe() method")
removed the call to part_init() in mmc.c, as this is done by the DM_MMC
framework.
However Allwinner is (still) relying on a non-DM MMC driver, so we are
now missing the implicit partition init, leading to failing MMC accesses
due to the missing partition information.

Bring the call back just for non-DM MMC driver to fix this regression.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Soeren Moch <smoch@web.de>
2019-01-09 07:13:30 -05:00
Philipp Tomsich
33502f371d rockchip: rk3399: fix missing braces in full pinctrl
Braces around the error-case for rk3399_pinctrl_set_pin_pupd lead to
an unconditional (and unintended) return from the function without it
ever setting pin-configurations.

Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-06 15:26:31 +01:00
Tom Rini
5324027566 TrueType fixes and documentation
-----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXC5WUQ4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXO9/AJ0R/Ze2CuvvFYb5ScnmtqVn524loQCdG9IgRcVs
 ZDgDWo68ZhCGDoWgLKo=
 =sRmZ
 -----END PGP SIGNATURE-----

Merge tag 'for-v2019.01' of git://git.denx.de/u-boot-video

TrueType fixes and documentation
2019-01-03 15:34:44 -05:00
Tom Rini
7436f5e54d Last-minute fixes for 2019.1:
- clamp DRAM size to below 32bit for 32bit targets to support 4GB
 - fix copyright notice on some Rockchip-contributed files
 - adjust vdd_log for the RK3399-Q7 to improve stability in some workloads
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcLfBzAAoJECaAFcEOcohNrMoH/ihFAiFblzVN7XPRTpV8+GGJ
 gsljC7DRGkgMT7IOnmCE+/44RGaQnP3bHQH6WG4zVHZ6vhrEyzqPaYzbzLg90ujj
 k1k4N6op3NA6e40FZvHzB/aglx1e5UFnWxstBpT1g82sL8xLSs0ubhsq6+gcr29I
 0qGTILHxwY95qUGDi2zlYNEwv5B0enlucfhB5kTZ7QYZX+Jz1SL4AI0sIapTdMg+
 /Bcu1Qi6B+xVklDhz9NUpYgst8T3J0Gabq7mqMXwommAgejsrjQWOnhDRrrWznd+
 OsJqEEo/TmdT/eqO7SffooKiEUPrw6YmKPtZAXkdlc8Cm+qZRvr/okozALBJizY=
 =v3QG
 -----END PGP SIGNATURE-----

Merge tag 'for-master-20190103' of git://git.denx.de/u-boot-rockchip

Last-minute fixes for 2019.1:
- clamp DRAM size to below 32bit for 32bit targets to support 4GB
- fix copyright notice on some Rockchip-contributed files
- adjust vdd_log for the RK3399-Q7 to improve stability in some workloads
2019-01-03 08:39:44 -05:00
Christoph Muellner
8188c83cfa rockchip: rk3399: Add Kconfig option for full pinctrl driver
This patch adds a Kconfig option to enable the full pinctrl driver
for the RK3399. This flag needs to be enabed in order to get the
features of the full pinctrl driver compiled in (i.e. a .set_state()
callback).

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:39:12 +01:00
Christoph Muellner
600888110d rockchip: rk3399: Add improved pinctrl driver.
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...

This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).

This patch has been tested on a RK3399-Q7 SoM (Puma).

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:39:04 +01:00
Christoph Muellner
5ff7768892 dm: pinctrl: Add pinctrl_decode_pin_config_dm().
pinctrl_decode_pin_config_dm() is basically a feature-equivalent
implementation of pinctrl_decode_pin_config(), which operates
on struct udevice devices and uses the dev_read_*() API.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:38:44 +01:00
Christoph Muellner
ddc824f89a power: regulator: Allow PWM regulator to be omitted from SPL.
This patch allows to enable the PWM regulator driver
independent for U-Boot and SPL.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:38:09 +01:00
Kever Yang
c43acfdc24 rockchip: ram: update license for sdram driver
Rockchip may use this sdram copy of source code for both open source
and internal project, update the license to use both GPL2.0+ and
BSD-3 Clause.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-02 22:37:10 +01:00
Tom Rini
695f67b5b3 Merge branch 'master' of git://git.denx.de/u-boot-spi 2019-01-02 14:20:29 -05:00
Nikolai Zhubr
cdf72c188c mtd: nand: raw: Add Hynix H27UBG8T2BTR id table
This patch adds Hynix H27UBG8T2BTR id table as part of raw nand,
these chips were available in some A20-olinuxino-micro boards.

Signed-off-by: Nikolai Zhubr <n-a-zhubr@yandex.ru>
[jagan: add proper commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-02 00:58:16 +05:30
Stefan Mavrodiev
5c1a87de58 spi: sun4i: Add rx_buf NULL pointer check
Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).

The patch add simple check if the destination pointer is NULL.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Jagan Teki <jagan@openedev.com>
[jagan: fix commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-02 00:54:05 +05:30
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
 -----BEGIN PGP SIGNATURE-----
 
 iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlwrbc8PHHNiYWJpY0Bk
 ZW54LmRlAAoJECjE2NMq1et3oCwL/RCqesqQaLKkUQDiYQJzoa6Ia7TeSTD1HoHl
 lYXarE9FloD7lHp4Lz1elU8Y+yTtjvixKS9UJGRc0pMcJJ/CEavjK+oBOVNbEnvH
 vm/oXQfZqj60tLc2Z7RfRe1gHHCcaGiBXJePea5WhP89cUZW1YBs4TVY2AIEQeRV
 V8vcxbBprqqBWyFRgH+ORsWrmkfcYEfiMr97Y8v07RRPX/C80e98PTc16fh9o7S1
 +i8Pcs0SIMnA8PqXVgrpa4DT7OS/ZtLADG/ODpvJ25nHoKvdhlXMc8o8L5dyaO1f
 66UD0A8D3PXkXkFodZujSjtKl5ygeA/4YkEnY6PRqd2W6kZsq6R7XCu/3e3eQSwK
 GFnWQnzLkDOCKMZlxR8l3sJdhY3Ee3oAQ+EX3PEy1MvKKrGA8PSOIKHq3tVNrPYB
 tBnJP32G+2Ya0SG169ROoUMZQQXfTt+9kdqsxx5xL2Pfpt9d+YinCM8uQdhqBGPa
 COqegLaD0ZkADsodZp876u3Irbo6bw==
 =mEcH
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Lukasz Majewski
acdf10e179 nand: vybrid: Extend the vf610 NFC NAND driver to support device tree (and DM)
This commit adds support for device tree and enumeration via device model
for the Vybrid's NFC NAND driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
8a12d127d7 Kconfig: Add entry for VF610 NAND NFC device tree aware driver
This commit provides code to add proper entry to Kconfig to enable
support for VF610 device tree aware driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
254409dbe8 nand: vybrid: Use calloc() instead of malloc() to allocate struct nfc
Without this change it is possible that Vybrid's NFC driver malloc() call
will obtain some memory used (and correctly free'd) by some previous
driver (in this case pinctrl for Vybrid).

As a result some fields of struct nfc - in out case mtd->_get_device - are
"pre initialized" with some random values.

On the latter stage of booting, when e.g. somebody calls 'mtdparts default'
the "data abort" is observed when __get_mtd_device() function is called.

The mtd->_get_device pointer is not NULL and wrong value is referenced.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-01 14:12:18 +01:00
Peng Fan
e3963c0943 drivers: ddr: introduce DDR driver for i.MX8M
Introduce DDR driver for i.MX8M. The driver will be used by SPL to
initialze DDR PHY and DDR Controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-01 14:12:18 +01:00
Peng Fan
cd357ad112 imx: rename mx8m,MX8M to imx8m,IMX8M
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
f0b73d9707 ARM: vybrid: Provide pinctrl driver for Vybrid (vf610)
This implementation comply with other iMX devices pinctrl drivers already
available in U-boot.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Martin Fuzzey
a2e99a71b2 w1: Add driver for i.MX bus master controller
Two variants of controllers are supported:
V1 (bitwise only) found in
	i.MX21, i.MX27, i.MX31, i.MX51
V2 (byte operations) found in
	i.MX25, i.MX35, i.MX50, i.MX53

Only tested on i.MX53 hardware but in both modes
(by modifying the device tree).

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
2019-01-01 14:12:18 +01:00
Xiaoliang Yang
da4918acb8 watchdog: imx: add config to disable wdog reset
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset
in imx_watchdog driver, so that the watchdog will not be fed in
u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01 14:12:18 +01:00
Xiaoliang Yang
005c1cf888 watchdog: driver support for fsl-lsch2
Support watchdog driver for fsl-lsch2. It's disabled in default.
If you want to use it, please enable CONFIG_IMX_WATCHDOG.
Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01 14:12:18 +01:00
Masahiro Yamada
94bf34b172 clk: uniphier: add NAND 200MHz clock
The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:38 +09:00
Masahiro Yamada
9d43649a77 mtd: rawnand: denali: fix a race condition when DMA is kicked
Based on Linux commit cf51e4b9c34407bf0c3d9b582b7837e047e1df47

Add the register read-back, commenting why this is necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:37 +09:00
Masahiro Yamada
8ccfbfb3e1 mtd: rawnand: denali: optimize timing parameters for data interface
Based on Linux commit 1dfac31a5a63ac04a9b5fbc3f5105a586560f191

This commit improves the ->setup_data_interface() hook.

The denali_setup_data_interface() needs the frequency of clk_x
and the ratio of clk_x / clk.

The latter is currently hardcoded in the driver, like this:

  #define DENALI_CLK_X_MULT       6

The IP datasheet requires that clk_x / clk be 4, 5, or 6.  I just
chose 6 because it is the most defensive value, but it is not optimal.
By getting the clock rate of both "clk" and "clk_x", the driver can
compute the timing values more precisely.

To not break the existing platforms, the fallback value, 50 MHz is
provided.  It is true for all upstreamed platforms.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:37 +09:00
Masahiro Yamada
a13fe7afe9 mtd: rawnand: denali_dt: add more clocks based on IP datasheet
Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5

Currently, denali_dt.c requires a single anonymous clock, but
the Denali User's Guide requires three clocks for this IP:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

This commit supports these named clocks to represent the real hardware.

For the backward compatibility, the driver still accepts a single clock
just as before.  The clk_x_rate is taken from the clock driver again if
the named clock "clk_x" is available.  This will happen only for future
DT, hence the existing DT files are not affected.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:36 +09:00
Simon Glass
b093753471 video: Add a default TrueType font
At present it is possible to enable TrueType support but not include any
fonts. This results in a blank display. Select Nimbus as the default font
to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-28 12:27:53 +01:00
Lokesh Vutla
e17e0ceb83 power: regulator: Return success on attempt to disable an always-on regulator
commit 4f86a724e8 ("power: regulator: denied disable on always-on
regulator") throws an error when requested to disable an always-on
regulator. It is right that an always-on regulator should not be
attempted to be disabled. But at the same time regulator framework
should not return an error when such request is received. Instead
it should just return success without attempting to disable the
specified regulator. This is because the requesting driver will
not have the idea if the regulator is always-on or not. The
requesting driver will always try to enable/disable regulator as
per the required flow. So it is upto regulator framework to not
break such scenarios.

Fixes: 4f86a724e8 ("power: regulator: denied disable on always-on regulator")
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-12-27 07:48:31 -05:00
Michal Simek
7b4ea2d888 phy: Fix u-boot coruption when fixed-phy is used
When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.

The patch is checking if address is in correct range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-26 21:35:52 -05:00
Lukasz Majewski
a7f4b4b344 dm: pinctrl: Prevent (re-)configuring pins when already done before relocation
This commit prevents from re-configuring pins if those were configured
before relocation.

Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-12-26 21:21:07 -05:00
Tom Rini
5c676780e1 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- stratix10 updates
2018-12-21 13:37:34 -05:00