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1351 commits

Author SHA1 Message Date
Sascha Hauer
c98b47ad24 core support for Freescale mx31
This patch adds the core support for Freescale mx31

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-03-30 11:30:43 +01:00
Sascha Hauer
8bf69d8178 Separate omap24xx specific code from arm1136
Move omap24xx code to cpu/arm1136/omap24xx, rename include/asm-arm/arch-arm1136 to cpu/arm1136/omap24xx.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-03-30 11:28:46 +01:00
Pieter Voorthuijsen
1377b5583a Removes all board specific code from the arch. part for DM644x (DaVinci) boards
Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-30 11:11:34 +01:00
Dirk Behme
1704dc2091 - Remove *_masked() functions as noted by Wolfgang
- Adapt register naming to recent TI spec (sprue26, March 2007)
- Fix reset_timer() handling
- As reported by Pieter [1] the overflow fix introduced a
delay of factor 16 (e.g 2 seconds became 32). While the
overflow fix is basically okay, it missed to divide udelay by
16, too. Fix this.
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179
- Remove software division of timer count value (DIV(x)
macro) and do it in hardware (TIM_CLK_DIV).
Many thanks to Troy Kisky <troy.kisky@boundarydevices.com>
and Pieter Voorthuijsen <pieter.voorthuijsen@Prodrive.nl> for
the hints & testing!

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

Acked-by: Pieter Voorthuijsen <pieter.voorthuijsen@Prodrive.nl>
2008-03-30 11:09:01 +01:00
Kumar Gala
dd6c910aad 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
79679d8002 85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
a5af4b358a 85xx: Fix merge duplication
ft_fixup_cpu() got duplicated in some merge snafu.  Remove the duplicate.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
a3e77fa535 85xx: Speed up get_ddr_freq() and get_bus_freq()
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
e9ea679918 85xx: Show DDR memory data rate in addition to the memory clock frequency.
Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
591933ca6e 85xx: get_tbclk() speed up and rounding fix
Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Kumar Gala
7aff0c051a 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:03 -05:00
Kumar Gala
ec2b74ffd3 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Bartlomiej Sieka
27f33e9f45 Merge branch 'new-image' of git://www.denx.de/git/u-boot-testing
Conflicts:

	common/cmd_bootm.c
	cpu/mpc8xx/cpu.c

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
2008-03-26 09:38:06 +01:00
Anton Vorontsov
7fa9cbb00d mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups
device_type = "soc" is being deprecated, newer device trees will use
"fsl,soc" and/or "fsl,immr" for the soc nodes.

This patch also adds clock-frequency property for soc nodes (the same
value as bus-frequency).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:48 -05:00
Anton Vorontsov
453316a2a1 83xx: serdes setup routines
This patch adds few routines to configure serdes on 837x targets.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:45 -05:00
Anton Vorontsov
a796cdf9c3 83xx: split COBJS onto separate lines
..plus get rid of some #ifdefs in the .c files.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25 19:16:44 -05:00
Michael Barkowski
5bbeea86eb mpc8323erdb: Improve the system performance
The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:44 -05:00
Wolfgang Denk
aa6f6d171a Coding Style cleanyp; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26 00:52:10 +01:00
Wolfgang Denk
6525489323 Merge branch 'master' of git://www.denx.de/git/u-boot-mips 2008-03-26 00:44:52 +01:00
André Schwarz
c512389cc4 MPC5200: support setup without FEC
Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is
defined. Systems without FEC, i.e. no FEC node in DTB, should be possible.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
2008-03-25 23:59:43 +01:00
Bryan O'Donoghue
77ff7b7444 8xx: Update OF support on 8xx
This patch does some shifting around of OF support on 8xx.

Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
2008-03-25 22:28:34 +01:00
Shinya Kuribayashi
373b16fc0c [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
d98e348e2e [MIPS] Fix dcache_status()
You can't judge UNCACHED by Config.K0 LSB.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
b0c66af53e [MIPS] Introduce _machine_restart
Handles machine specific functions by using weak functions.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
decaba6f5c [MIPS] Cleanup CP0 Status initialization
Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
d43d43ef28 [MIPS] Initialize CP0 Cause before setting up CP0 Status register
Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
2613862323 [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init()
Move things to appropriate place.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:07 +09:00
Shinya Kuribayashi
ccf8f824ef [MIPS] Implement flush_cache()
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
2e0e5271aa [MIPS] Fix I-/D-cache initialization loops
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.

In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
1898840797 [MIPS] Replace memory clearance code with f_fill64
This routine fills memory with zero by 64 bytes, and is 64-bit capable.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
2f5d414ccb [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros
This patch replaces the current function definitions with NESTED, LEAF
and END macro. They specify some more additional information about the
function; an alignment of symbol, type of symbol, stack frame usage, etc.
These information explicitly tells the assembler and the debugger about
the types of code we want to generate.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 21:30:06 +09:00
Shinya Kuribayashi
e1390801a3 [MIPS] Request for the 'mips_cache_lock()' removal
The initial intension of having mips_cache_lock() was to use the cache
as memory for temporary stack use so that a C environment can be set up
as early as possible.

But now mips_cache_lock() follow lowlevel_init(). We've already have the
real memory initilaized at this point, therefore we could/should use it.
No reason to lock at all.

Other problems:

Cache locking is not consistent across MIPS implementaions. Some imple-
mentations don't support locking at all. The style of locking varies -
some support per line locking, others per way, etc. Some parts use bits
in status registers instead of cache ops. Current mips_cache_lock() is
not necessarily general-purpose.

And this is worthy of special mention; once U-Boot/MIPS locks the lines,
they are never get unlocked, so the code relies on whatever gets loaded
after U-Boot to re-initialize the cache and clear the locks. We're sup-
posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented,
but leave the situation as it is for a long time.

For these reasons, I proposed the removal of mips_cache_lock() from the
global start-up code.

This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that
*things have changed*. If he wants the same behavior as before, he needs
to have CFG_INIT_RAM_LOCK_MIPS in his config file.

If we don't have any regression report through several releases, then
we'll remove codes entirely.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Acked-by: Andrew Dyer <amdyer@gmail.com>
2008-03-25 11:39:29 +09:00
Yuri Tikhonov
b73a19e160 LWMON5: POST RTC fix
Modify the RTC API to provide one a status for the time reported by
the rtc_get() function:
  0 - a reliable time is guaranteed,
< 0 - a reliable time isn't guaranteed (power fault, clock issues,
      and so on).

The RTC chip drivers are responsible for providing this info if the
corresponding chip supports such functionality. If not - always
report that the time is reliable.

The POST RTC test was modified to detect the RTC faults utilizing
this new rtc_get() feature.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-20 21:48:46 +01:00
Stefan Roese
71665ebf88 ppc4xx: Add Canyonlands NAND booting support
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.

This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.

Tested with 512 byte page NAND device (32MByte) on Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Stefan Roese
2801b2d2a9 ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Stefan Roese
8ac41e3e37 ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
56e4101783 ppc4xx: interrupt.c reworked
This patch is a rework of the 4xx interrupt handling done while
adding the 460EX/GT support. Interrupts are needed on 4xx for the
EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
84a999b6cd ppc4xx: program_tlb now uses 64bit physical addess
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
c3307fa186 ppc4xx: miiphy.c reworked
While adding the 460EX/GT support I reworked the 4xx miiphy code. It
badly neede some cleanup.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Marian Balakowicz
7e492d8258 Merge branch 'master' of git://www.denx.de/git/u-boot into new-image 2008-03-12 12:23:02 +01:00
Mike Nuss
74eb022259 PPC4xx (Sequoia): Fix Ethernet "remote fault" problems
Every now and then a Sequoia board (or equivalent hardware) had
problems connecting to a Gigabit capable network interface.

There were differences in the PHY setup between Linux and U-Boot.

This patch fixes the problem. Apparently "remote fault" is being set,
which signals to some devices (on the other end of the cable) that a
fault has occurred, while other devices ignore it. I believe the RF bit
was causing the issue, but I removed T4 also, to match up with Linux.

Signed-off-by: Mike Nuss <mike@terascala.com>
2008-03-04 08:55:27 +01:00
Stefan Roese
76957cb3d6 ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
currently 4k/2k is configured. This patch fixes this issue.

Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-02 22:49:27 +01:00
Wolfgang Denk
093e14c522 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2008-03-02 21:46:20 +01:00
John Rigby
5f91db7f58 MPC5121e ADS PCI support take 3
Adds PCI support for MPC5121

Tested with drivers/net/rtl8139.c

Support is conditional since PCI on old silicon does not work.

ads5121_PCI_config turns on PCI

In this version, condition compilation of PCI code has been moved
from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
suggested by Jean-Christophe PLAGNIOL-VILLARD

Signed-off-by: John Rigby <jrigby@freescale.com>
2008-03-02 21:44:59 +01:00
Anatolij Gustschin
4fae35a53b ppc4xx: Fix problem in 4xx_enet.c driver
U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is
enabled. To reproduce the problem ensure that 'ethrotate'
environment variable isn't set to "no" and then run
"tftp 200000 not_existent_file".
This patch tries to fix the issue.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-03-02 21:34:55 +01:00
Marian Balakowicz
e18489e8c2 Merge branch 'master' of git://www.denx.de/git/u-boot into new-image 2008-02-29 13:56:44 +01:00
Kumar Gala
2b22fa4bae 85xx: Don't icbi when unlocking the cache
There is no reason to icbi when invalidating the temporary stack in
the d-cache.  Its impossible on e500 to have the i-cache contain
any addresses in the temp stack and it can be problematic in generating
transactions on the bus to non-valid addresses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-02-27 16:30:47 -06:00
Andy Fleming
534ea6b6f8 Fix source for ECM error IVPR
The source vector for the ECM was being set to 2,
but that's what the source vector for DDR was being
set to.  Change it to 1.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-02-27 16:28:57 -06:00