Commit graph

4344 commits

Author SHA1 Message Date
Simon Glass
8ba1ade3f8 rockchip: gru: Add more devicetree settings
This adds some devicetree settings for the Gru-based boards, based on
what works on a Kevin board.

Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
Make the u-boot.rom file intended to be flashed on it match its size.
Add properties for booting from SPI, and only try to boot from SPI as
MMC and SD card don't seem to work in SPL yet.

The Chromium OS EC needs a delay between transactions so it can get
itself ready. Also it currently uses a non-standard way of specifying
the interrupt. Add these so that the EC works reliably.

The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
property to find the panel it should work on. Add the property for the
Gru-based boards.

The U-Boot GPIO controlled regulator driver only considers the
"enable-gpios" devicetree property, not the singular "enable-gpio" one.
Some devicetree source files have the singular form as they were added
to Linux kernel when it used that form, and imported to U-Boot as is.
Fix one instance of this in the Gru boards' devicetree to the form that
works in U-Boot.

The PWM controlled regulator driver complains that there is no init
voltage set for a regulator it drives, though it's not clear which one.
Set them all to the voltage levels coreboot sets them: 900 mV.

The RK3399 SoC needs to know the voltage level that some supplies
provides, including one fixed 1.8V audio-related regulator. Although
this synchronization is currently statically done in the board init
functions, a not-so-hypothetical driver that does this dynamically would
query the regulator only to get -ENODATA and be confused. Make sure
U-Boot knows this supply is at 1.8V by setting its limits to that.

Most of this is a reapplication of commit 08c85b57a5 ("rockchip: gru:
Add extra device-tree settings") whose changes were removed during a
sync with Linux at commit 167efc2c7a ("arm64: dts: rk3399: Sync
v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
they don't get lost again.

Signed-off-by: Simon Glass <sjg@chromium.org>
[Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-03-18 18:12:03 +08:00
Tom Rini
f5ac18f406 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: dts: turris_mox: fix non-working network / MDIO (Marek)
2022-03-16 08:12:45 -04:00
Marek Behún
351729ca44 arm: mvebu: dts: turris_mox: fix non-working network / MDIO
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke network on Turris MOX, because the SOC's MDIO bus in
U-Boot currently isn't probed via DM as it's own device, but is
registered as part of mvneta's driver, which means that pinctrl
definitions are not parsed for the MDIO bus node. Also mvneta driver
does not consider "phy-handle" property, only "phy".

For now, fix this by adding armada-3720-turris-mox-u-boot.dtsi file
returning the MDIO to how it was defined previously.

A better solution (using proper mvmdio DM driver) is being work on, but
will need testing on various boards, and we need the bug fixed now for
the upcoming release.

Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-16 07:24:28 +01:00
Marek Vasut
19fbe102b2 ARM: dts: stm32: Add DFU support for DHCOM recovery
This patch configures U-Boot SPL for DHCOM SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.

The DFU usage procedure is identical to STM32MP1 DHCOR SoM, see commit
3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery") ,
except for switching the SoM into DFU mode. By default, the DHCOM SoM
has no dedicated mechanism for setting BOOTn straps into UART/USB mode,
therefore to enter DFU mode, the SoC must fail to boot from boot media
which can be selected by the BOOTn strap override mechanism first and
then fall back to DFU mode.

In case of a SoM with pre-populated BOOTn strap override button, power
the system off, remove microSD card (if applicable), hold down the BOOTn
strap override button located between eMMC and SoM edge connector, power
on the SoM. The SoC will fail to boot from SD card and fall back into
DFU mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:20:32 +01:00
Marek Vasut
9a8996df05 ARM: dts: stm32: Move vdd_io extras into Avenger96 extras
The vdd_io regulator is present only on DHCOR SoM configured for 1V8 IO,
as populated on Avenger96, but not present on 3V3 DHCOR SoM. Move these
extras to Avenger96 u-boot DT extras.

Fixes: 3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-03-15 09:15:10 +01:00
Marek Vasut
27f6c653ae ARM: dts: stm32: Add USB OTG pinctrl and regulator nodes into SPL DT on DHCOR
Fix the following warning in SPL and make sure that even DTs which
enforce Vbus detection using u-boot,force-vbus-detection;, the DFU
in SPL will work.

dwc2-udc-otg usb-otg@49000000: prop pinctrl-0 index 0 invalid phandle

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:13:31 +01:00
Patrick Delaunay
182738fe2f arm: dts: stm32mp15: alignment with v5.17
Device tree alignment with Linux kernel v5.17-rc1
- ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins
  on STM32MP15 DKx boards
- ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
- ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:11:47 +01:00
Pali Rohár
037bb6e2ca arm: a37xx: Remap IO space to bus address 0x0
Remap PCI I/O space to the bus address 0x0 in the Armada 37xx device-tree
in order to support legacy I/O port based cards which have hardcoded I/O
ports in low address space.

Some legacy PCI I/O based cards do not support 32-bit I/O addressing.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-14 14:04:18 +01:00
Jan Kiszka
39834ccdd4 arm: dts: iot2050: Add cfg register space for ringacc and udmap
Recent unrelated fixes (9876ae7db6) revealed that we were missing bits
from 2af181b53e in the IOT2050 dt. Add them, but only for main U-Boot.
SPL loads from QSPI only, thus cannot use DMA.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2022-03-04 15:20:06 -05:00
Tom Rini
d274f92246 First set of u-boot-atmel fixes for the 2022.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmIgkpAcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyDmXCACMc7jIpdFEz2NKTnSy
 hudLhzWTQ8NrPFrOkxAJREMaMhRCh5b/5AW0469fFFZ86NxpgHyuoNJtnflN/V8t
 ucVfM3/fJgfoyBnfyzv+Cuju8DQNGZZnBrYKBeIKzlD8/nwX0Ah/xbGb/IKCD3cT
 IVl8UqXh57NDVYApb/04sDK1hNfjex3jYejH/l8pQYiF/fsfYQI9XPGdD0w4N6N1
 D1Rtpmr9lJqJiq7xjCIwHoqigYV4E7lu5P4Uk9RzxBOo8BAcrn10DMgjlg9AL4F/
 LqmLCTC65myV5tqrdVES6EHke7S3QD9vi6qB4qB/tr/AE3c/4cdzGUL7nkyzI1Cq
 iZlg
 =9HIi
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-fixes-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91

First set of u-boot-atmel fixes for the 2022.04 cycle:

This fixes set includes only a single fix for the Ethernet on sama7g5ek
board which is broken at the moment.
2022-03-03 08:24:37 -05:00
Michael Walle
554a85313b board: sl28: use fit image generator
Simplify the binman config and fdt nodes by using the "@..-SEQ"
substitutions and CONFIG_OF_LIST.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:01:02 +05:30
Tom Rini
17a0dc6abf Merge branch '2022-02-21-platform-updates'
- Assorted updates / fixes for Apple, TI and Aspeed platforms
2022-02-21 08:53:24 -05:00
Suman Anna
5d90836cb5 arm: dts: k3-j7200: Fix up MAIN R5FSS cluster mode back to Split-mode
The default U-Boot environment variables and design are all set up for
the MAIN R5FSS cluster to be in Split-mode. This is the setting used
when the dts nodes were originally added in v2021.01 U-Boot and the
dt nodes are synched with the kernel binding property names in
commit 468ec2f3ef ("remoteproc: k3_r5: Sync to upstreamed kernel DT
property names") merged in v2021.04-rc2.

The modes for the MAIN R5FSS cluster got switched back to LockStep mode
by mistake in commit fa09b12dc5 ("arm: ti: k3: Resync dts files and
bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the
following warning messages when early-booting the cores using default
env variables,

k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode
Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed!

Fix this by switching back both the clusters to the expected Split-mode.
Make this mode change in the u-boot specific dtsi file to avoid such
sync overrides in the future until the kernel dts is also switched to
Split-mode by default.

Fixes: fa09b12dc5 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14")
Signed-off-by: Suman Anna <s-anna@ti.com>
2022-02-21 08:35:40 -05:00
Keerthy
da6a8d9c28 arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max voltages of VDD_CPU
Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU
minimum voltage is .6V & maximum voltage is .9V.

Correct the same. While at it fix the comment to reflect VDD_CPU
instead of VDD_MPU.

Data Sheet Link: https://www.ti.com/lit/gpn/dra829v

Signed-off-by: Keerthy <j-keerthy@ti.com>
2022-02-21 08:35:40 -05:00
Tom Rini
24b628a8f8 Xilinx changes for v2022.04-rc3
microblaze:
 - Fix exception handler
 
 zynqmp:
 - Show information about secure images
 - DT changes (som u-boot file removal)
 - Fix zynqmp_pm_cfg_obj_convert.py
 - Fix platform boot
 
 xilinx:
 - Fix bootm_size calculation
 - Remove GPIO_EXTRA_HEADER selection
 
 power:
 - Add zynqmp power management driver
 
 scsi:
 - Add phy support to ceva driver
 
 zynq qspi:
 - Fix unaligned accesses and check baudrate setup
 - Add support for spi memory operations
 
 net:
 - Fix 64bit calculation in axi_emac
 
 video:
 - Add missing gpio dependency for seps driver
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYhOKGwAKCRDKSWXLKUoM
 IQP/AJ9U6inecbFh6LWchwX1ByhHVB0NuQCeLExfpcscdJlVUtNBC8kaRrrdjVM=
 =nq1B
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
2022-02-21 08:32:02 -05:00
Michal Simek
9bd4232f95 arm64: zynqmp: Remove additional gpio header from dlc21
This header shouldn't be in this file and there is already pointer to
dt-bindings/gpio/gpio.h.

Fixes: d2d14383ba ("arm64: zynqmp: Add support for DLC21 (Smartlynq+) board")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/266bc91073f1149f3f60b1c9c0ba509c48470e2e.1644911870.git.michal.simek@xilinx.com
2022-02-21 13:21:22 +01:00
Marek Vasut
fea6607317 ARM: imx: imx8mn-ddr4-evk: Add ethernet support
Add support for ethernet on the imx8mn-ddr4-evk.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-19 23:32:23 +01:00
Tim Harvey
2cb156e126 board: gateworks: venice: add imx8mn-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
 - LPDDR4 DRAM
 - eMMC FLASH
 - Gateworks System Controller
 - LTE CAT M1 modem
 - USB 2.0 HUB
 - M.2 Socket with USB2.0, PCIe, and dual-SIM
 - IMX8M FEC
 - PCIe based GbE
 - RS232/RS485/RS422 serial transceiver
 - GPS
 - CAN bus
 - WiFi / Bluetooth
 - MIPI header (DSI/CSI/GPIO/PWM/I2S)
 - PMIC

To add support for the i.MX8M Nano GW7902:
 - Add imx8mn-venice dts/defconfig/include
 - Add imx8mn-gw7902 dts
 - Add imx8mn-2gb lpddr4 dram configs
 - Add misc support for IMX8M Nano SoC
 - rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific
 - update README with differences for IMX8MN vs IMX8MM

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-19 14:46:54 +01:00
Ying-Chun Liu (PaulLiu)
ddb56f371a arm: imx8m: add support for Advantech RSB-3720
Add initial support for Advantech RSB-3720 board.
The initial support includes:
 - MMC
 - eMMC
 - I2C
 - FEC
 - Serial console

Signed-off-by: Darren Huang <darren.huang@advantech.com.tw>
Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw>
Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw>
Signed-off-by: Tim Liang <tim.liang@advantech.com.tw>
Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
2022-02-19 14:46:54 +01:00
Patrick Wildt
e72cb770d4 arm: dts: imx8mq: add MNT Reform 2
Device tree taken from Linux v5.16-rc5.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-18 18:12:23 +01:00
Tom Rini
8ad1c9c26f Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- a37xx: pci: Cleanup and minor fix for root port check (Pali)
- pci: mvebu: Ensure that root port is always on root zero bus (Pali)
- kwbimage: Fix dumping DATA registers for v0 images (Pali)
- kwbimage: Support for parsing extended v0 format (Pali)
- a37xx: Fix code and update DTS files to upstream version (Pali)
- a37xx: Fix and extend building memory map (Pali)
- ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision (Marek)
- mvebu: Optionally reset board on DDR training failure (Marek)
2022-02-17 11:03:50 -05:00
Pali Rohár
0934dddc64 arm: a37xx: Update DTS files to version from upstream Linux kernel
This change updates all Armada 37xx DTS files to version which is used by
Linux kernel v5.18.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
6560bf4ede arm: a37xx: espressobin: Explicitly enable eMMC node in -u-boot.dtsi
Official DT bindings for Espressobin have disabled eMMC node.

As U-Boot requires to have this node enabled by default, do it in
armada-3720-espressobin-u-boot.dtsi DTS file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
a134aaa54e arm: a37xx: espressobin: Move U-Boot specific partitions node to -u-boot.dtsi
U-Boot specific changes should be in armada-3720-espressobin-u-boot.dtsi DTS file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
9dde7a09fc arm: a37xx: Update sdhci pointers to official DT bindings
In Linux kernel version of armada-37xx.dtsi file sdhci1 pointer refers to
sdhci@d0000 node and sdhci0 pointer to sdhci@d8000 node.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
0c4625ac7d watchdog: armada_37xx: Convert to official DT bindings
Official DT bindings have only one reg property: watchdog address space.
Convert armada-37xx-wdt.c driver to offical DT bindings and access sel_reg
register via MVEBU_REGISTER() macro, as its value (required by U-Boot
driver) is not in DT yet. In later stage can be driver cleaned to not use
it.

This change would allow U-Boot to use A3720 watchdog DTS structure from
Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
af6d0938f3 usb: ehci: ehci-marvell: Update compatible string to official DT bindings
Official DT bindings use compatible string marvell,armada-3700-ehci.
Update drivers and DTS files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
9bc68546bb phy: marvell: a3700: Update compatible string to official DT bindings
In commit d368e10705 ("phy: marvell: a3700: Convert to official DT
bindings in COMPHY driver") was done update to official DT bindings but
compatible string of official DT bindings was not updated.

Fix it now.

Fixes: d368e10705 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Sinthu Raja
bc2972bd9a arm: dts: k3-j721e-r5-sk: Update R5 DT to pick the new DDR config
A new lpddr4 configuration is introduced for J7 SK with 4266 MTs data
rate. Therefore, update the R5 DTS file to point to the new DDR config
file.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
51f660120f arm: dts: k3-j721e-sk: EMIF tool update to 0.6.1 with 4266MTs for lpddr4
EMIF tool for J721E SK is now updated to 0.6.1 that includes
* Updated write DQ training pattern to enable user pattern and clock
  pattern (from 0x7 to 0x6).
* Updated IO drive strength to 40-80-80 Ohms.

J721E SK uses the lpddr4 configuration of 4266 MTs data rate which is
the same as J721E EVM but facing random failures. As the tool update is
specific to the SK board, add a new lpddr4 config of 4266 MTs.

Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
daad7d6d85 arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk
Add R5 specific dts for J721E-SK

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
58d61fb5a7 arm: dts: k3-j721e-sk: Add initial A72 specific dts support
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
performance vision accelerators, video codec accelerators, latest C71x
and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
dedicated safety island and security accelerators. The SoC is power
optimized to provide best in class performance for industrial and
automotive applications.

    J721E SK supports the following interfaces:
    * 4 GB LPDDR4 RAM
    * x1 Gigabit Ethernet interface
    * x1 USB 3.0 Type-C port
    * x3 USB 3.0 Type-A ports
    * x1 PCIe M.2 E Key
    * x1 PCIe M.2 M Key
    * 512 Mbit OSPI flash
    * x2 CSI2 Camera interface (RPi and TI Camera connector)
    * 40-pin Raspberry Pi GPIO header

Add A72 specific dts for J721E-SK.

[1] https://www.ti.com/tool/SK-TDA4VM

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
1157f36724 arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C
Board ID I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for wakup_i2c0 on which
board ID EEPROM is connected.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Felix Brack
9f0deae6d5 arm: pdu001: Fix dt to work with the current am33xx dtsi files
The changes introduced with commit 6337d53fdf ("arm: dts: sync am33xx
with Linux 5.9-rc7") prevent the PDU001 from operating correctly.
This patch fixes the configuration of the pin multiplexer and uart3.

Signed-off-by: Felix Brack <fb@ltec.ch>
2022-02-14 13:04:39 -05:00
Sinthu Raja
ad41ed1208 arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
* disabled Write DQ training
* improve CA ODT to 60 ohms

The lpddr4 enabled with periodic WDQ training is causing periodic 26us
stall. This makes the SoC stall without doing anything which leads to
R5 interrupt latency in TCM memory. Due to this periodic training there
are some outstanding CPU transactions waiting for the lpddr4 to complete.

Hence, disable the periodic write DQ training during the
non-initialization stage of lpddr4 which results in an approximate 1us
stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms

The rationales are as follows:
- PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling,
  disable bit 1 that supports Write DQ during non-initialization to
  avoid ~26us stall during code execution.

- MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes
  the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by
  increasing the signal swing.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-10 17:17:39 -05:00
Rasmus Villemoes
3609e1dc5f dts: automatically build necessary .dtb files
When building for a custom board, it is quite common to maintain a
private branch which include some defconfig and .dts files. But to
hook up those .dts files requires modifying a file "belonging" to
upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch
to a newer upstream then often results in a conflict which, while it
is trivial to resolve by hand, makes it harder to have a CI do "try to
build our board against latest upstream".

The .config usually includes information on precisely what .dtb(s) are
needed, so to avoid having to modify the Makefile, simply add the
files in (SPL_)OF_LIST to dtb-y.

A technicality is that (SPL_)OF_LIST is not always defined, so rework
the Kconfig symbols so that (SPL_)OF_LIST is always defined (when
(SPL_)OF_CONTROL), but only prompted for in the cases which used to be
their "depends on".

nios2 and microblaze already have something like this in their
dts/Makefile, and the rationale in commit 41f59f6853 is similar to
the above. So this simply generalizes existing practice. Followup
patches could remove the logic in those two makefiles, just as there's
potential for moving some common boilerplate from all the
arch/*/dts/Makefile files to the new scripts/Makefile.dts.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:26:12 -07:00
Aswath Govindraju
a94d70ad37 arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:04 -05:00
Aswath Govindraju
3c1d89ff76 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:03 -05:00
Keerthy
57b02b79f3 dts: am57xx*: Add ipu early boot DT changes
Add support for ipu early boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
5717294230 arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
5329c548eb arm: dts: dra7: Add ipu and related nodes
Add ipu and the associated nodes.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
0bfc701e67 dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodes
Add all the ipu early boot related nodes

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Aswath Govindraju
81fb00b884 arm: dts: k3-j721s2-ddr: Add DDR support
J721S2 can support two instances for DDR. Therefore, add the device support
for the same and use 4266MT/s as DDR frequency.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
626a2fdb98 arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
a9d8cf24a4 arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                 Common Processor Board

Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.

Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
05d441a713 arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
2bab70ed04 arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.

Some highlights of this SoC are:

* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.

See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28

Introduce basic support for the J721S2 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-08 09:41:27 -05:00
Marcel Ziswiler
2bc2f817ce board: toradex: add verdin imx8m plus support
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB
IT V1.0B module. They are strapped to boot from eFuses which are factory
fused to properly boot from their on-module eMMC. U-Boot supports
booting from the on-module eMMC only, SDP support is disabled for now
due to missing i.MX 8M Plus USB support.

Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet both on-module eQoS and FEC (requires PHY on carrier board)
- GPIOs
- I2C

Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper

ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.

Boot:
U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
Quad die, dual rank failed, attempting dual die, single rank configuration.
Normal Boot
WDT:   Started watchdog@30280000 with servicing (60s timeout)
Trying to boot from BOOTROM
Find img info 0x&48025a00, size 872
Need continue download 1024
Download 779264, Total size 780424
NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
NOTICE:  BL31: Built : 16:52:37, Aug 26 2021

U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)

CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
Reset cause: POR
DRAM:  8 GiB
Core:  78 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog@30280000 with servicing (60s timeout)
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
Setting variant to wifi
Net:   Hard-coding pdata->enetaddr
eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
Hit any key to stop autoboot:  0
Verdin iMX8MP #

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-07 16:33:22 +01:00
Michal Simek
af98bf62fa arm64: zynqmp: Remove SOM *u-boot.dtsi
Disable mmc from u-boot.dtsi file because it was there only for kv260
board. With kr260 this is not needed because we will switch to full DT per
board with SD/EMMC there too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3440d9f94361b4800658f313a5785f43ee84ecf3.1642590109.git.michal.simek@xilinx.com
2022-02-07 10:37:21 +01:00
Heiko Thiery
16c7369ede board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-02-05 15:49:02 +01:00