Commit graph

1192 commits

Author SHA1 Message Date
Michal Simek
fcbdd7a070 .mailmap: Start to use new amd.com email address
Xilinx has been acquired by AMD that's why emails should be also updated.
The patch is updating .mailmap file and also MAINTAINERS files as was done
by commit 5cd1ecb994 ("ppc: qemu: Update MAINTAINERS for correct email
address").
The rest of my emails are not going to change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-04-19 14:51:11 -04:00
Tom Rini
2ddf84679d u-boot-imx-20220413
i.MX patches for 2022.07
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11710
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYlaYFg8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76Y1RQCgjI6iHC1yb0245e2RoV3VIeib9mEAoIUKX3yE
 HbvZYN8YZbQHlNOiSOZo
 =z3fU
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20220413' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220413

i.MX patches for 2022.07

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11710
2022-04-13 08:00:11 -04:00
Tim Harvey
8479b9e6c9 drivers: misc: add Gateworks System Controller driver
Add a driver for the Gateworks System Controller used on Gateworks boards
which provides a boot watchdog, power control, temperature monitor,
and voltage ADCs.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-04-12 15:36:17 +02:00
Gaurav Jain
6a8829ae13 update CAAM MAINTAINER
updated CAAM driver files maintainer.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-04-12 11:20:30 +02:00
Ivan Vozvakhov
067cfc1c2e led: led_pwm: Add a driver for LEDs connected to PWM
Add a driver which allows to use of LEDs connected
to PWM (Linux compatible).
MAINTAINERS: add i.vozvakhov as a maintainer of leds-pwm
C(required during new functionality adding).

Signed-off-by: Ivan Vozvakhov <i.vozvakhov@corp.mail.ru>
2022-04-11 11:39:19 -04:00
Patrick Delaunay
fd52e7f9c7 rng: add OP-TEE based Random Number Generator
Add driver for OP-TEE based Random Number Generator on ARM SoCs
where hardware entropy sources are not accessible to normal world
and the RNG service is provided by a HWRNG Trusted Application (TA).

This driver is based on the linux driver: char/hw_random/optee-rng.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-04-11 10:28:04 -04:00
Tom Rini
037ef53cf0 Xilinx changes for v2022.07-rc1 v2
xilinx:
 - Allow booting bigger kernels till 100MB
 
 zynqmp:
 - DT updates (reset IDs)
 - Remove unneeded low level uart initialization from psu_init*
 - Enable PWM features
 - Add support for 1EG device
 
 serial_zynq:
 - Change fifo behavior in DEBUG mode
 
 zynq_sdhci:
 - Fix BASECLK setting calculation
 
 clk_zynqmp:
 - Add support for showing video clock
 
 gpio:
 - Update slg driver to handle DT flags
 
 net:
 - Update ethernet_id code to support also DM_ETH_PHY
 - Add support for DM_ETH_PHY in gem driver
 - Enable dynamic mode for SGMII config in gem driver
 
 pwm:
 - Add driver for cadence PWM
 
 versal:
 - Add support for reserved memory
 
 firmware:
 - Handle PD enabling for SPL
 - Add support for IOUSLCR SGMII configurations
 
 include:
 - Sync phy.h with Linux
 - Update xilinx power domain dt binding headers
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYkxUZwAKCRDKSWXLKUoM
 IXJ2AKCQcoFK7wanCCvZfuEJCSwO5E4eCACginE2CFVXKcY1P8ta4ESusjY2TH0=
 =HOoS
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
2022-04-05 11:27:39 -04:00
Tom Rini
4de720e98d Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05 08:33:32 -04:00
Samuel Holland
e9e87ec47c tools: mkimage: Add Allwinner TOC0 support
Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.

A TOC0 image is composed of a header and two or more items. One item
is the firmware binary. The others form a chain linking the firmware
signature to the root-of-trust public key (ROTPK), which has its hash
burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.

The pseudo-ASN.1 structure is manually assembled; this is done to work
around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
implementation has been verified to work with the A50, A64, H5, H6,
and H616 SBROMs, and it may work with other SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
b799eabc7e sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:23:50 +01:00
Tom Rini
8221c52d88 First set of u-boot-at91 features for the 2022.07 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmJH28ocHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyDv4B/9FBx95f7zR6WmguG05
 VyBchjphsRSuXHb7NieVNNEIpCJu+zw8YutngN2Q8KWIbM9o1OZnrNGxuKR9s+Px
 ivMXytGGsIa74XXhxv2boX151R1a5TG4UPf4Vn20qxmUiScE4FaoW5wQHG2vGqxd
 /LbzENNCA1A41/RGGysqyY8nQgOEY+Iass+OaHe7XjngcCfY5oY4IRqJ/Ak7ojkv
 Vm46i+KCTuyBlcMDjAwDsukSmzsujz2FyzZU1Uy62N8quEdXgrlIA/Yh4oarZ+BO
 5W/BJe1rClbnBkMJJn71GUlmnYrioYeUvxvIYwZWooe0Hgr+Iv1vOXv8aJ4hBsdc
 yoje
 =SwGu
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.07 cycle:

This feature set includes the new driver for the Atmel TCB timer,
alignment in DT for sama7g5 and sama7g5ek board, one Kconfig conversion
for external reset, and the usage of Galois tables from ROM for sama5d2
device.
2022-04-04 08:26:55 -04:00
Sean Anderson
c8f4cc9590 arm: smh: Add semihosting entry to MAINTAINERS
These files are spread all over the tree, so just use a regex. Orphaned
for now, since this is more of a "one-off" series. Though I'll be happy
to review patches.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Clément Léger
70fb1ae9dd timer: atmel_tcb_timer: add atmel_tcb driver
Add a driver for the timer counter block that can be found on sama5d2.
This driver will be used when booting under OP-TEE since the pit timer
which is part of the SYSC is secured. Channel 1 & 2 are configured to
be chained together which allows to have a 64bits counter.

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-04-01 15:42:46 +03:00
Michal Simek
fb92cc2c17 pwm: Add driver for cadence TTC
TTC has three modes of operations. Timer, PWM and input counters.

There is already driver for timer under CADENCE_TTC_TIMER which is used for
ZynqMP R5 configuration.
This driver is targeting PWM which is for example configuration which can
be used for fan control.
The driver has been tested on Xilinx Kria SOM platform where fan is
connected to one PL pin. When TTC output is connected via EMIO to PL pin
TTC pwm can be configured and tested for example like this:
pwm config 0 0 10000 1200
pwm enable 0 0
pwm config 0 0 10000 1400
pwm config 0 0 10000 1600

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/915a662ddb88f7a958ca1f307e8fea59af9d7feb.1634303847.git.michal.simek@xilinx.com
2022-03-30 14:50:47 +02:00
Tom Rini
34d2b7f203 Prepare v2022.04-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmJBxXQACgkQFHw5/5Y0
 tywKKAv+L+sCmqfJ4Zy2cdzWkGZI3NZMWi8yzUUU37RH5I+3Blht+z6dMslm9gCB
 7/PwS5y7WH3l3wEdeXcw4FUCgNh3D8YyfCcVCsQ0Qxig49xwWz8Jn6t+haOWD6eW
 uXim+gSG+ceWTBrKf3InzXN5fHPIcF66r+k3opwAwIYKpT8p8CgM4ewshBCAsc6t
 6qSLf+A64JNv/y2DTS+sPDY68tnplbyRvrNb6YEazOF6b6SnSE2j+EH8RkIZ+2yT
 cTUhQ2o9JJIKnaG9MTqHB+XVe80oPB7bTWInFo2JxGn98XeS7CTCcnDZhLqWrvHF
 gBfcpEcVE2blVbg/Vo2x4rnU1dop44ch6pE9k5SPFJcPdlzdwFHHgGyfGi9LtD4K
 JAvaIQdz6ZEOQqShpCxcbL/g2/uoRaXFqC7E8IE+WdFMXGBQoZpqaoBMoefnyplk
 xrzqaQye38JgZDX0ku4cm4SMArAfr4sVHcdDlSlzY3y2KQ8Ead25irRvq7GoQ2Ad
 Odo9taQF
 =9g2Y
 -----END PGP SIGNATURE-----

Merge tag 'v2022.04-rc5' into next

Prepare v2022.04-rc5
2022-03-28 12:36:49 -04:00
Johan Jonker
ba366809bc MAINTAINERS: add rockchip regex for more files and directories
The current files and directories with wildcard patterns for
Rockchip patches in MAINTAINERS is not always complete.
Add the regex for DT related files and a generic regex for
catching some other forgotten cases, so that the maintainers
receive all Rockchip related patches.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-03-18 18:12:03 +08:00
Tom Rini
297e6eb8dc Xilinx changes for v2022.07-rc1
microblaze:
 - Add support for reserved memory
 
 xilinx:
 - Update FRU code with MAC reading
 
 zynqmp:
 - Remove double AMS setting
 - DT updates (mostly for SOMs)
 - Add support for zcu106 rev 1.0
 
 zynq:
 - Update nand binding
 
 nand:
 - Aligned zynq_nand to upstream DT binding
 
 net:
 - Add support for ethernet-phy-id
 
 mmc:
 - Workaround CD in zynq_sdhci driver also for ZynqMP
 - Add support for dynamic/run-time SD config for SOMs
 
 gpio:
 - Add driver for slg7xl45106
 
 firmware:
 - Add support for dynamic SD config
 
 power-domain:
 - Update zynqmp driver with the latest firmware
 
 video:
 - Add skeleton driver for DP and DPDMA
 
 i2c:
 - Fix i2c to work with QEMU
 
 pinctrl:
 - Add driver for zynqmp pinctrl driver
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYjIBkgAKCRDKSWXLKUoM
 IYUwAKCYRBxb59BFq4MRvTbNcRZ7H4oGIQCfVUl3x9KZ7nFZaYAaBXFBxwna+PE=
 =irCR
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver
2022-03-16 12:52:02 -04:00
Huang Jianan
2c30aa3dbc test/py: Add tests for the erofs
Add Python scripts to test 'ls' and 'load' commands, as well as
test related filesystem functions.

Signed-off-by: Huang Jianan <jnhuang95@gmail.com>
2022-03-15 16:19:51 -04:00
Huang Jianan
739941e11e fs/erofs: add filesystem commands
Add 'ls' and 'load' commands.

Signed-off-by: Huang Jianan <jnhuang95@gmail.com>
2022-03-15 16:19:29 -04:00
Huang Jianan
830613f8f5 fs/erofs: add erofs filesystem support
This patch mainly deals with uncompressed files.

Signed-off-by: Huang Jianan <jnhuang95@gmail.com>
2022-03-15 16:19:29 -04:00
Damien Le Moal
fd426b3106 k210: use the board vendor name rather than the marketing name
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15 17:43:11 +08:00
Tom Rini
2abf048ab7 Prepare v2022.04-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmIvp/8ACgkQFHw5/5Y0
 tyyI6wwApR++p9BBlWEZn1B5sivCXcs9oCX3Vs8vegpiiRbs/pGsyKV6pfEHHYV5
 lhw1YNZ0accKmqBmX19tdpQ2ZzHq3+g0eGJL8xioXU3hRoZZNsDewAF8KS+aHPpk
 qMuA+xbDi08I6z2qtrIpaDd//DO2jAkFF+/TKOzSgUSxBaomQiziZaB2x28bIBH2
 zsLMP4vzZ03uCSZVSd7HMBz0qiGhioJo5Ch2eU4TTJW19CXeMTAuav6SDq+6vJGi
 cIUe31YEe742jOVmtf2RuJQ+mDjsEfT11wvRajcbOlH/Ho7E5iFxQkmOEThpvybE
 YD5d5uLLpQj42PfBpSvx4nMJcvyOmqxdizUJxCgi/q5HrhdzcO6LwLLON0T4W4zG
 Vsue+iTjOKXgLdD8g/VogL38iHxhpfY7zsFB98vvHcoLwhEXvfvhO8Dj/lwLw4Ic
 88B6uz3TqAPNqSnTWphJPCwG8STwyqlvLXwTF+eICbtQW3uuHEtnmlsXQJeFmdUa
 fGK8dUfr
 =wyE5
 -----END PGP SIGNATURE-----

Merge tag 'v2022.04-rc4' into next

Prepare v2022.04-rc4
2022-03-14 17:40:36 -04:00
Ashok Reddy Soma
dbd673f14d pinctrl: zynqmp: Add pinctrl driver
Add pinctrl driver for Xilinx ZynqMP SOC. This driver is compatible with
linux device tree parameters for configuring pinmux and pinconf.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d7eefa83c8c0129f7243a25de56a289e948f6c6.1645626183.git.michal.simek@xilinx.com
2022-03-14 15:23:31 +01:00
Simon Glass
9de3773a5c event: Add a script to decode the event-spy list
For debugging and dicoverability it is useful to be able to see a list of
each event spy in a U-Boot ELF file. Add a script which shows this, along
with the event type and the source location. This makes events a little
easier to use than weak functions, for example.

Add a basic sandbox test as well. We could provide a test for other
boards, but for now, few use events.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Simon Glass
c81b460c86 event: Add a command
Add a command to show the available events.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Simon Glass
7d02645fe4 event: Add a simple test
Add a test for event registration and activation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Simon Glass
87a5d1b5d0 event: Add basic support for events
Add a way to create and dispatch events without needing to allocate
memory. Also add a way to 'spy' on events, thus allowing 'hooks' to be
created.

Use a linker list for static events, which we can use to replace functions
like arch_cpu_init_f(). Allow an EVENT_DEBUG option which makes it
easier to see what is going on at runtime, but uses more code space.

Dynamic events allow the creation of a spy at runtime. This is not always
necessary, but can be enabled with EVENT_DYNAMIC if needed.

A 'test' event is the only option for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Michal Simek
a744a284e3 net: phy: Add support for ethernet-phy-id with gpio reset
Ethernet phy like dp83867 is using strapping resistors to setup PHY
address. On Xilinx boards strapping is setup on wires which are connected
to SOC where internal pull ups/downs influnce phy address. That's why there
is a need to setup pins properly (via pinctrl driver for example) and then
perform phy reset. I can be workarounded by reset gpio done for mdio bus
but this is not working properly when multiply phys sitting on the same
bus. That's why it needs to be done via ethernet-phy-id driver where dt
binding has gpio reset per phy.

DT binding is available here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml

The driver is are reading the vendor and device id from valid phy node
using ofnode_read_eth_phy_id() and creating a phy device.
Kconfig PHY_ETHERNET_ID symbol is used because not every platform has gpio
support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Link: https://lore.kernel.org/r/70ab7d71c812b2c972d48c129e416c921af0d7f5.1645627539.git.michal.simek@xilinx.com
2022-03-09 12:43:16 +01:00
Michal Simek
d24b3e32ab MAINTAINERS: Remove duplicated entry for ehci-zynq.c
ehci-zynq.c is assigned to Zynq and ZynqMP that's why remove one.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d97779178fa56f1c6af40f5604b0bf349002cd36.1646639027.git.michal.simek@xilinx.com
2022-03-09 12:42:31 +01:00
Stefan Roese
a12366a807 MAINTAINERS: Add watchdog maintainers entry
I've been handling "inofficially" the watchdog related patches for a few
years now. Let's make this official and add a tree for it and also add
myself here in the MAINTAINERS file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Harald Seiler <hws@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-03-08 07:23:10 +01:00
T Karthik Reddy
15efe0f3a5 gpio: slg7xl45106: Add support for slg7xl45106 i2c gpo expander
slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by
writing and reading corresponding gpo bit value into its data register.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michael Walle
07d6cb9378 gpio: add sl28cpld driver
The gpio block is part of the sl28cpld sl28cpld management controller.
There are three different flavors: the usual input and output where the
direction is configurable, but also input only and output only variants.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 11:59:35 +05:30
Michael Walle
f606c9a895 watchdog: add sl28cpld watchdog driver
The watchdog timer is part of the sl28cpld management controller. The
watchdog timer usually supervises the bootloader boot-up and if it bites
the failsafe bootloader will be activated. Apart from that it supports
the usual board level reset and one SMARC speciality: driving the
WDT_TIMEOUT# signal.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 11:59:35 +05:30
Michael Walle
42595eb706 misc: add sl28cpld base driver
Add a multi-function device driver which will probe its children and
provides methods to access the device.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 11:59:35 +05:30
Tom Rini
24b628a8f8 Xilinx changes for v2022.04-rc3
microblaze:
 - Fix exception handler
 
 zynqmp:
 - Show information about secure images
 - DT changes (som u-boot file removal)
 - Fix zynqmp_pm_cfg_obj_convert.py
 - Fix platform boot
 
 xilinx:
 - Fix bootm_size calculation
 - Remove GPIO_EXTRA_HEADER selection
 
 power:
 - Add zynqmp power management driver
 
 scsi:
 - Add phy support to ceva driver
 
 zynq qspi:
 - Fix unaligned accesses and check baudrate setup
 - Add support for spi memory operations
 
 net:
 - Fix 64bit calculation in axi_emac
 
 video:
 - Add missing gpio dependency for seps driver
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYhOKGwAKCRDKSWXLKUoM
 IQP/AJ9U6inecbFh6LWchwX1ByhHVB0NuQCeLExfpcscdJlVUtNBC8kaRrrdjVM=
 =nq1B
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
2022-02-21 08:32:02 -05:00
Michal Simek
e0283cbdfd power: zynqmp: Add power domain driver for ZynqMP
Driver should be enabled by CONFIG_POWER_DOMAIN=y and
CONFIG_ZYNQMP_POWER_DOMAIN=y. Power domain driver doesn't have own DT node
but it uses zynqmp firmware DT node that's why there is a need to bind
driver when firmware node is found.

Driver itself is simple. It is sending pmufw config object overlay for
enabling access to device which is done in ...domain_request().
In ...domain_on() capabilities are passed and node is requested.
This should be bare minimum of required to get power domain driver working.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Link: https://lore.kernel.org/r/f4b9433b91c0b18c375b061c7a4e29d428f70547.1644226055.git.michal.simek@xilinx.com
2022-02-15 13:01:42 +01:00
AKASHI Takahiro
118a0ecd6d tools: mkeficapsule: add man page
Add a man page for mkeficapsule command.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-02-11 20:07:55 +01:00
Pali Rohár
ba4e6f8a5e MAINTAINERS: Update list of Armada 385 and Armada 3720 drivers
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-10 07:12:16 +01:00
Keerthy
57b02b79f3 dts: am57xx*: Add ipu early boot DT changes
Add support for ipu early boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
0bfc701e67 dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodes
Add all the ipu early boot related nodes

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
fc6b41fefb remoteproc: ipu: Add driver to bring up ipu
The driver enables IPU support. Basically enables the clocks,
timers, watchdog timers and bare minimal MMU and supports
loading the firmware from mmc.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix compile warnings]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
795b2c476f reset: dra7: Add a reset driver
Add a reset driver to bring IPs out of reset.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 09:41:27 -05:00
Simon Glass
c77504df68 acpi: Add myself as maintainer
Add myself as maintainer of the generic ACPI code, until someone else
steps up to take it on.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Anastasiia Lukianenko
800f0d05e1 MAINTAINERS: Update e-mail in Xen maintainership
Changing e-mail because of leaving EPAM.

Signed-off-by: Anastasiia Lukianenko <vicooodin@gmail.com>
Reviewed-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
2022-01-24 10:35:10 -05:00
Tom Rini
068415eade Xilinx changes for v2022.04-rc1
gpio:
 - Add modepin driver
 
 net:
 - Save random mac addresses to eth variable
 
 zynqmp gem:
 - Add support for mdio bus DT description
 - Add support for reset and SGMII phy configuration
 - Reduce timeout for MDIO accesses
 
 zynqmp clk:
 - Fix clock handling for gem and usb
 
 phy:
 - Add zynqmp phy/serdes driver
 
 serial:
 - Add one missing compatible string
 
 microblaze:
 - Symbol alignement
 - SPL fixups
 - Code cleanups
 
 zynqmp:
 - Various dt changes, DP pre-reloc, gem resets, gem clocks
 - Switch SOM to shared psu configuration
 - Move dcache handling to firmware driver
 - Workaround gmii2rgmii DT description issue
 - Enable broadcasts again
 - Change firmware enablement logic
 - Small adjustement in firmware driver
 
 versal:
 - Support new mmc@ DT nodes
 - Fix run time variable handling
 - Add missing I2C_PMC ID for power domain
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYeg7sQAKCRDKSWXLKUoM
 IVhJAKCAiNx/joEeFBJ0XgThtJzFhCjdMwCfYKY9Ewz4L0n2I56lDgR3UJroct0=
 =HtB+
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
2022-01-19 11:43:44 -05:00
Heinrich Schuchardt
bf59c46bcb MAINTAINERS: remove Alexander Graf from EFI PAYLOAD
The last review by Alex was in 2019.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15 10:57:22 +01:00
Mark Kettenis
ee327d1d93 watchdog: Add a driver for the Apple watchdog
This driver supports the watchdog timer found on Apple's M1 SoC.
On systems that use these SoC, the watchdog timer is the primary
way to reboot the system.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Michal Simek
1d78d68349 phy: zynqmp: Add serdes/psgtr driver
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.

USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2022-01-12 10:41:46 +01:00
T Karthik Reddy
3b441cf4e4 zynqmp: gpio: Add support for zynqmp gpio modepin driver
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Tom Rini
4afab30cae Prepare v2022.01-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmHArDwACgkQFHw5/5Y0
 tyzxyAv/SjZjoEwG8nu7ptVZqTsZfm+tVwwWmQEBAA40MXy/KSccDtbUwB5GCO6f
 Uvk+qFFDbCkbGZh5VKbQusMmUoB02Xu9zUoSxKxcXL4WfC6Bg5GV/UWN9s8G3Tm6
 4wcP0l8WFcQjjr89UfXugiZH58psvFu6PBbWVY4rMH9gZ5ds0AkNOF0L+HbdVmMR
 a5HBfrcySRY2kiTQuKF+RVlMW6BtaOqJp/XIyy8w6bH09ykMomj/u7z3JP3y9ZzL
 w3FXqCLlIEnvdDcqfWvfjoJ/gm0WcLulgSVpTFGS0jgJpnbeAURtZcuVgj6aPRUW
 FRon+u0tj3wpFjibs2cpyXWd+gw/bLLFpDXx78AUAPjxG31tEKbnR1j8R8wBZJ0B
 TqWZ3pCne/LPOT90y2KW2z6ty2n/yEn6qEFFT9MN9R4L0N+U0er//sYJC/nn/e6u
 fjvQ9OPLbnAfHVrad3ZeIkePrLOIF6XYwNQpsjt9aE2kU9IvV5sTa8TxZuQgasBU
 A46FgXtC
 =MEG2
 -----END PGP SIGNATURE-----

Merge tag 'v2022.01-rc4' into next

Prepare v2022.01-rc4
2021-12-20 17:12:04 -05:00