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power: zynqmp: Add power domain driver for ZynqMP
Driver should be enabled by CONFIG_POWER_DOMAIN=y and CONFIG_ZYNQMP_POWER_DOMAIN=y. Power domain driver doesn't have own DT node but it uses zynqmp firmware DT node that's why there is a need to bind driver when firmware node is found. Driver itself is simple. It is sending pmufw config object overlay for enabling access to device which is done in ...domain_request(). In ...domain_on() capabilities are passed and node is requested. This should be bare minimum of required to get power domain driver working. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/f4b9433b91c0b18c375b061c7a4e29d428f70547.1644226055.git.michal.simek@xilinx.com
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commit
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6 changed files with 151 additions and 0 deletions
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@ -634,6 +634,7 @@ F: drivers/mtd/nand/raw/zynq_nand.c
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F: drivers/net/phy/xilinx_phy.c
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F: drivers/net/zynq_gem.c
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F: drivers/phy/phy-zynqmp.c
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F: drivers/power/domain/zynqmp-power-domain.c
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F: drivers/serial/serial_zynq.c
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F: drivers/reset/reset-zynqmp.c
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F: drivers/rtc/zynqmp_rtc.c
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@ -8,6 +8,7 @@
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <log.h>
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#include <zynqmp_firmware.h>
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#include <asm/cache.h>
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@ -226,8 +227,27 @@ static const struct udevice_id zynqmp_firmware_ids[] = {
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{ }
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};
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static int zynqmp_firmware_bind(struct udevice *dev)
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{
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int ret;
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struct udevice *child;
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if (IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) {
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ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
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"zynqmp_power_domain",
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dev_ofnode(dev), &child);
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if (ret) {
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printf("zynqmp power domain driver is not bound: %d\n", ret);
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return ret;
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}
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}
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return dm_scan_fdt_dev(dev);
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}
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U_BOOT_DRIVER(zynqmp_firmware) = {
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.id = UCLASS_FIRMWARE,
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.name = "zynqmp_firmware",
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.of_match = zynqmp_firmware_ids,
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.bind = zynqmp_firmware_bind,
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};
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@ -88,4 +88,13 @@ config TI_POWER_DOMAIN
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help
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Generic power domain implementation for TI K3 devices.
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config ZYNQMP_POWER_DOMAIN
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bool "Enable the Xilinx ZynqMP Power domain driver"
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depends on POWER_DOMAIN && ZYNQMP_FIRMWARE
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help
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Generic power domain implementation for Xilinx ZynqMP devices.
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The driver should be enabled when system starts in very minimal
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configuration and it is extended at run time. Then enabling
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the driver will ensure that PMUFW enable access to requested IP.
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endmenu
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@ -16,3 +16,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
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obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
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obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
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obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
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obj-$(CONFIG_ZYNQMP_POWER_DOMAIN) += zynqmp-power-domain.o
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89
drivers/power/domain/zynqmp-power-domain.c
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89
drivers/power/domain/zynqmp-power-domain.c
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@ -0,0 +1,89 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021, Xilinx. Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <misc.h>
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#include <power-domain-uclass.h>
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#include <linux/bitops.h>
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#include <zynqmp_firmware.h>
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#define NODE_ID_LOCATION 5
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static unsigned int xpm_configobject[] = {
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/* HEADER */
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2, /* Number of remaining words in the header */
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1, /* Number of sections included in config object */
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PM_CONFIG_OBJECT_TYPE_OVERLAY, /* Type of Config object as overlay */
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/* SLAVE SECTION */
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PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
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1, /* Number of slaves */
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0, /* Node ID which will be changed below */
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PM_SLAVE_FLAG_IS_SHAREABLE,
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PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK |
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PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK |
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PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
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};
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static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
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const u32 qos, const enum zynqmp_pm_request_ack ack)
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{
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return xilinx_pm_request(PM_REQUEST_NODE, node, capabilities,
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qos, ack, NULL);
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}
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static int zynqmp_power_domain_request(struct power_domain *power_domain)
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{
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/* Record power domain id */
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xpm_configobject[NODE_ID_LOCATION] = power_domain->id;
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zynqmp_pmufw_load_config_object(xpm_configobject, sizeof(xpm_configobject));
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return 0;
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}
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static int zynqmp_power_domain_free(struct power_domain *power_domain)
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{
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/* nop now */
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return 0;
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}
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static int zynqmp_power_domain_on(struct power_domain *power_domain)
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{
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return zynqmp_pm_request_node(power_domain->id,
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ZYNQMP_PM_CAPABILITY_ACCESS,
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ZYNQMP_PM_MAX_QOS,
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ZYNQMP_PM_REQUEST_ACK_BLOCKING);
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}
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static int zynqmp_power_domain_off(struct power_domain *power_domain)
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{
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/* nop now */
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return 0;
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}
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struct power_domain_ops zynqmp_power_domain_ops = {
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.request = zynqmp_power_domain_request,
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.rfree = zynqmp_power_domain_free,
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.on = zynqmp_power_domain_on,
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.off = zynqmp_power_domain_off,
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};
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static int zynqmp_power_domain_probe(struct udevice *dev)
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{
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return 0;
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}
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U_BOOT_DRIVER(zynqmp_power_domain) = {
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.name = "zynqmp_power_domain",
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.id = UCLASS_POWER_DOMAIN,
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.probe = zynqmp_power_domain_probe,
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.ops = &zynqmp_power_domain_ops,
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};
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@ -371,4 +371,35 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
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int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
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u32 arg3, u32 *ret_payload);
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/* Type of Config Object */
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#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
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#define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U
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/* Section Id */
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#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
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#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
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/* Flag Option */
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#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
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#define PM_MASTER_USING_SLAVE_MASK 0x2U
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/* IPI Mask for Master */
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#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
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#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
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#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
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enum zynqmp_pm_request_ack {
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ZYNQMP_PM_REQUEST_ACK_NO = 1,
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ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
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ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
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};
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/* Node capabilities */
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
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#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
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#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
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#define ZYNQMP_PM_MAX_QOS 100U
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#endif /* _ZYNQMP_FIRMWARE_H_ */
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