In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].
What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.
The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).
This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
- H3-ES2.0-Salvator-X
- M3-ES1.1-Salvator-XS
- M3N-ES1.1-ULCB
[1] 8719ca8113 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df24 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")
[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0
[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id Linux commit summary line
9925e8795726801 pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6 pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78 pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919 pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48 pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9 pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49 pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043 pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269 pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
The TI Davinci (da850/l138/am1808) use pinctrl-single,bits for
pinmuxing peripherals. This patch allosw the pinctrl-single
driver to parse the pinctrl-single,bits options and correctly
setup devices.
Signed-off-by: Adam Ford <aford173@gmail.com>
Update .bind callback in order to bind all pinctrl subnodes
with "gpio-controller" property to gpio_stm32 driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
if (*idx < 0)
^
drivers/pinctrl/pinctrl_stm32.c: At top level:
warning: no previous prototype for 'stm32_pinctrl_probe' [-Wmissing-prototypes]
int stm32_pinctrl_probe(struct udevice *dev)
^~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice CHOTARD <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB
- pinctrl: meson: add support for getting pinmux status
- pinctrl: meson-g12a: add support for drive-strength-microamp property
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJdARHoAAoJEHfc29rIyEnRT/oP/1SXqPLazLQapLPr82nFh5f3
Wf/YxmzWscpWFsS3eyOuIpitIY4d461UWRR3i855uY0TFfoJlt1doIsJWyMy5fTm
XLUSoZrSzWPPfdcdXyVfQ3LvA/+r67hfxq0CQjABpCMa/ewn9hV8lPp7Yuz3ZxRm
xZQi52j/9idl6i0z17wPHef2bbgskZW56eYG9BJxmHDNIboJlaEOF0vwNb9SenfL
uWOSPSEL7MbKm3c1EtDo1KPilU2des0MOxrrkM/kLpMyoOnGwML/GQuRdKUzGhFC
CHoP74WCWvoyJtlqDizhYdXHkT15Kg1HZyegbp/vw8u52Ol1R5eSXZxp82VlP7Zm
KPvC2tL6RIbx4+uGD3abwsY3nEAne4IRB9Kj0EaX4nKu/nZpKo44qbzPLBUpGFF8
kD28/vrOlXqunYQIwon/1lQ3yfzceXqe2f60KZz7chv3u5c23xOpiWx1ptGetKHm
kiJtRofb+6HsiGJPRny7DS1/6zPzKLe1gJdWs5ZSOCm2nl0Nd1YMCe0J444lgk1m
iEbT5K9GjEV8g4BpQdFGCWy89pb4whUwFxz8+AYykqfEJSG6xjCW2Wp8N1Sfk1VF
1CKMd93c+39BwxJTDyQlp+2zi4wOZnIuQ080tzk1hMh2CzZ/ZWjiXquidZI12uw+
vRopJDiqYGX30TnHMhCm
=QA+5
-----END PGP SIGNATURE-----
Merge tag 'u-boot-amlogic-20190612' of git://git.denx.de/u-boot-amlogic
- pinctrl: meson-gx: fix GPIO_TEST_N and GPIOCLK_ groups
- pinctrl: meson-gxbb: add hdmi related pins to fix HDMI on GXBB
- pinctrl: meson: add support for getting pinmux status
- pinctrl: meson-g12a: add support for drive-strength-microamp property
The GXBB pinctrl is missing pins related to HDMI, namely hot plug
detection (hpd) and I2C (sda + scl).
This fixes HDMI support for GXBB in u-boot.
Reported-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mohammad Rasim <mohammad.rasim96@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
add drive-strength bank regiter and bit value for G12A SoC
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
drive-strength-microamp is a new feature needed for G12A SoC.
the default DS setting after boot is usually 500uA and it is not enough for
many functions. We need to be able to set the drive strength to reliably
enable things like MMC, I2C, etc ...
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to support the "pinmux status" command, use the common functions
to get the pins count and names, and add the AXG specific function to get
the current function from registers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to support the "pinmux status" command, use the common functions
to get the pins count and names, and add the GX specific function to get
the current function from registers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
In order to support the "pinmux status" command, add common function
to get pins count and pin name.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The GPIO_TEST_N was in the wrong pmx group table, move it back with the AO
groups, GPIODV_18 was missing, add it back, and finally the GPIOCLK_*
group names were missing.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is necessary to be able to re-use the pinctrl code in early
SPL to properly configure pins.
The problem is that those "static" structures (without explicit
initialization) are placed in the SDRAM area, which corresponds to
u-boot proper (not even SPL).
Hence, when one wants to configure pins before relocation via DTS/DM,
the board hangs (imx6q SoC powered one) as only OCRAM area is available
(0x009xxxxx).
This commit prevents from this issue by moving the imx6_pinctrl_soc_info
structure to data section (from BSS).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This reverts commit 502980914b.
This is a superseded version, revert this to apply new patch set.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This function is now replaced by common pin controller GPIO configuration
functionality, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Implement the gpio_request_enable/gpio_disable_free callbacks to let
the GPIO driver call the pin control framework and let it reconfigure
pins as GPIOs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Add missing cfg->type = PINMUX_TYPE_GPIO upon successfully setting pin
as a GPIO to retain the pin configuration information.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
Add callback to configure, and de-configure, pin as a GPIO on the
pin controller side. This matches similar functionality in Linux
and aims to replace the ad-hoc implementations present in U-Boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
-----BEGIN PGP SIGNATURE-----
iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlzDBtoPHHNiYWJpY0Bk
ZW54LmRlAAoJECjE2NMq1et3UpQL/ipaUejQOOr00oOgUBQqt3JCPZ7KNu8ruih/
nIFUDrI8nP+4psaOhRp1sEPFJUxUjdIqODeAZD8zrlEi1pXNAgPWYrFRfbz54bzw
jLsqqMz1/djQseLydQTcqZTSz8Ys7o+8OfKH64fdsZn+y9no9tHBN5hz5qWdXexN
kbyykkg8TJC3eUyRZqKuULOqzDV9BAdASOXu7UTa04sEekLdVvS2+zkUdB6UVZTN
LOAzm+7xY8Tey1BZxLuZUJDpHzFEMvPvlbbQRrxeDn/feZJwNgIP6hGcMeVOwOIf
KEwFn/m/HI2JWS4taXb5aT+v3xmiQvyCC3jNW0XTf5rq02pbfgyPsVhGQIGyU2yY
Fj7zIN7hVCLJNBpctvXyuAd1MjOlGEPIrHNjRnIZjtr7/iA1AIRn7Hg4cGNCHw6V
5gdza3B/xFODN+Ts6O+UVIukI61MJ6mGGdNCueOnWDviNROOL82D7Jh02KfNNNxR
q+yPsHSpo6rC1MGXv4SOReZtgpng/w==
=CzWQ
-----END PGP SIGNATURE-----
Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
Porting to DM and i.MX8
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
Add pinctrl support for the Amlogic G12A SoC, which is
very similar to the Amlogic AXG support but with an additionnal
drive-strength register bank.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlyxBfcACgkQfxc6PpAI
reYtsgf8DSi0h6bNmoPGA8q/aRTQii2x6TheT+AonvND4Kt5ycyw5Otjn3n7O13G
ubDvBn3Ix5znRaj6nSip7zO1M59dNB19Qk5i+ad21w3rx2V8HTWcLYMwUmC2DPZU
qMaOpIeEWYKuCDFRhpw/b6yF1rtq4lMxWTrSlB+ewntmrKV+Ymk0UWYSCfNMmZ8F
cLSd/wFWoTxysZLT4t/5jbNIPU8XaO0hYH0C9Y/tsK80bCpdjkTMNQuO7/qlgUb9
E7BCf1HXuMqWTZuqub9hu1y24PYufNSHziK1R+lNqm+yW3MxJGihP5OsCfVoHDgu
FU+QIKeBo64R3eH1VSrAh8pLp143bg==
=4/BU
-----END PGP SIGNATURE-----
Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm
fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAlywtKQACgkQKPlOlyTy
XBgYbBAAlRLhN52f2vv9Hng/tfCAuZk7c9tJ+b/5i36ZoJNozeaiOBgwVl3eeEa9
v4SeKz4J+9FJLOSZkIPrCvX+HaACQn7Pqw/64h3JE8TEzfU5lgmV4Xk2dcXtkmEL
L5PTQoNMZDgQaeltLtN29yIW5lVxx0NUN9O0FLY5+R/ptXlCFaAGdgSuXH36boDR
/cvfLlaZPM/hA7l3wRUjWa17L8MNEon4+cqLkzDyTTihdHOdZA4P1O7ce/XffGQp
BAiSta4EztB1xs0oTAOEmUJp1v8Ae7yRuFoZaCp+Dgq+0WOTbxDW4J57fTaphES1
su3yoYjju+M/dUb/sWmOQNjeIchJPYWcpiOl9E8jQ/l2SaBJ6Oxmg7PxC3Ww0X2z
JdF6mcKeaDH3WYO20FeC6xb9Q9FN2yX4rcW/Yg46TdeJ3T2sj8A19ZCHoeAQRl0I
68SbAaDJw/K3fTBFPd9VyQQQawPbyhmpdQAOWtixNWBFIBbZpqI4o1DMJKJRoxqd
Ail++ysLUICB0XXg0rGI+dFusjcu9AAeRODc11dtGa0YBh2Y28JrJ4OuV14GYQhe
5J8BquRaDADA3iK/+3C6TUSQGhb5pFXTcsdNBC9zBPb/ePeMDfZxBcB2vCOnZDZ1
m0kR5qnsz4IH8/rCmJ5wmMBh6JuyPoCSdiTVuuU5CuCVGYbmJuE=
=NrV8
-----END PGP SIGNATURE-----
Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips
- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Some binding define child node gpio-controller without compatible property.
This patch avoid to bind the pinconfig uclass to these node.
For example, the binding for st,stm32-pinctrl
(./device-tree-bindings/pinctrl/st,stm32-pinctrl.txt) defines the GPIO
controller/bank node as sub-node of pincontrol (st,stm32f429-pinctrl)
but without compatible (as it is not mandatory).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In case of system with several pin-controller device, probe the first
UCLASS_PINCTRL by seq number (defined by alias) to avoid race condition
with I2C PINCONTROL driver for GPIO expander (GPIO expander need I2C bus,
I2C driver need PINCONFIG).
Signed-off-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit 5ff7768892.
As noted in the comment, the function pinctrl_decode_pin_config_dm()
only served as a temporary solution.
Since the function has no users anymore, we can remove it again.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Periphs bank offset must be applied on all pins and
PMX bank to prevent issue in meson_pinconf_set call.
Without offset on pins when a call to pinconf is done
meson_gpio_calc_reg_and_bit return wrong offset.
To avoid breaking pmx function offset is needed in pmx bank structure too.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
