Commit graph

66490 commits

Author SHA1 Message Date
Ilko Iliev
8794cb543f arm: dts: imx7: Fix error in coresight TPIU graph connection
OF graph endpoint connections must be bidirectional and dtc warn if they
are not. i.MX7 based DTs have an error and generate
warnings:

arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/replicator/ports/port@0/endpoint: graph connection to node
'/soc/tpiu@30087000/port/endpoint' is not bidirectional
arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/soc/tpiu@30087000/port/endpoint: graph connection to node
'/replicator/ports/port@1/endpoint' is not bidirectional

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2020-07-16 11:20:58 +02:00
Lukasz Majewski
949feef062 arm: Add extra boot device (UART) to run Ymodem u-boot.img boot on XEA (imx28)
This commit enables imx28 based XEA board's u-boot.sb (SPL) to download
u-boot proper (u-boot.img) via Ymodem protocol.

This is extremely useful in the recovery scenario where u-boot.sb is
downloaded via uuu utility to SDRAM [*], and then one can upload u-boot
proper via serial console to fully debrick the device.

Note - debricking procedure of imx28 devices:
- NXP's original USB based tools (like mxsldr or uuu) expect single
  u-boot.sb which is a relic of the old U-Boot (~2013) without SPL and
  U-Boot proper distinction.

[*] On Host:
------------
cat << EOF > imx28_xea.lst
uuu_version 1.3.0
SDPS: boot -f /srv/tftp/xea/u-boot.sb
SDPU: done
EOF

Please start picocom:
sudo picocom -b 115200 -s "sz -vv" /dev/ttyUSB1
sudo ./uuu/uuu -V imx28_xea.lst

On the U-boot console one shall see:
Trying to boot from UART
CCC

Then please press CTRL+A, S
and type u-boot.img

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-07-16 11:20:33 +02:00
Heiko Schocher
08556f829f imx6: aristainetos: sync defconfig with 2020.10
as patch
gpio: search for gpio label if gpio is not found through bank name

is now in mainline, but functionality is disabled, we
need to enable

CONFIG_DM_GPIO_LOOKUP_LABEL

for the aristainetos boards.

Signed-off-by: Heiko Schocher <hs@denx.de>
2020-07-16 11:20:27 +02:00
Mo, Yuezhang
ee6866e6c7 watchdog: imx: Support set timeout by wdt command
After "4b969deac0 watchdog: imx: Add DM support", the imx watchdog
can be started by wdt command. But the imx watchdog driver only
support start with the default timeout.

This commit adds the support for setting the timeout which pass from
the wdt command into the imx watchdog. If the timeout out of the
valid range(0.5~128s), start the watchdog with a timeout within the
valid range and the timeout is the one which closest to the passed
timeout.

Signed-off-by: Yuezhang.Mo <yuezhang.mo@sony.com>
Reviewed-by: Andy.Wu <Andy.Wu@sony.com>
Reviewed-by: stefano Babic <sbabic@denx.de>
2020-07-16 11:20:21 +02:00
Sébastien Szymanski
eefd93e7f8 power: pmic_pca9450: fix PCA9450A I2C address
Quoting Ye Li from NXP:

    "We have confirmed with PMIC team, 0x35 is used only on early chips
    and not used any more. 0x25 is the final address."

Fix it by merging power_pca9450a_init and power_pca9450b_init into one
function power_pca9450_init.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-07-16 11:20:14 +02:00
Heinrich Schuchardt
90865614b4 ARM: mx6: make CAAM usable on the i.MX6 boards
Even if the HAB fuse is not set we want to be able to use the Cryptographic
Accelerator and Assurance Module (CAAM) for generating random numbers. So
SYS_FSL_HAS_SEC should be selected even if IMX_HAB is not set.

arch_misc_init() has to be called to initialize the CAAM.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-16 11:20:08 +02:00
Fabio Estevam
496cb1f274 pico-imx6ul: Fix Quick Start Guide URL
The current URL for the pico imx6ul board is not valid anymore. Change
to a different URL that works.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-07-16 11:20:02 +02:00
Ye Li
6103e570cd gpio: mxc_gpio: Improve to use ofdata_to_platdata
Current mxc_gpio DM driver allocates the platdata in bind function to
handle both OF_CONTROL enabled case and disabled case. This implementation
puts the devfdt_get_addr in bind, which introduces much overhead especially
in board_f phase.

Change the driver to a common way for handling the cases by using
ofdata_to_platdata and using DM framework to allocate platdata.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-07-16 11:19:57 +02:00
Ye Li
dfbdaa66b7 misc: scu_api: Add SCFW API to get the index of boot container set
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-07-16 11:19:50 +02:00
Ye Li
def88bce09 spi: fsl_qspi: Support to use full AHB space on i.MX
i.MX platforms provide large AHB mapped space for QSPI, each
controller has 256MB. However, current driver only maps small
size (AHB buffer size) of AHB space, this implementation
causes i.MX failed to boot M4 with QSPI XIP image.

Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX)
to address above problem.

When the config is set:
1. Full AHB space is divided to each CS.
2. A dedicated LUT entry is used for AHB read only.
3. The MODE instruction in LUT is replaced to standard ADDR instruction
4. The address in spi_mem_op is used to SFAR and AHB read

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-07-16 11:19:43 +02:00
Ye Li
93d6c8f7b7 spi: fsl_qspi: Add support for i.MX7ULP
Add compatible string and driver data for i.MX7ULP.
Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should
align with 1KB, because the lowest 10 bits are reserved by the
registers definition.
For i.MX7ULP which has only 128Bytes AHB buffer, must align it
when setting the registers and selecting cs.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-07-16 11:19:36 +02:00
Niel Fourie
26a6ed1b2e arm: imx6q: pcm058: Convert pcm058 to use DM with DTs
Convert pcm058 support to use device trees and the driver model.
Add rudimentary boot scripts to the environment, expand README.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Niel Fourie
7e64182ef4 arm: imx6q: pcm058: change MAINTAINER
Change the MAINTAINER of pcm058.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Niel Fourie
08310cf96e arm: dts: imx6q: Add Linux dts files for Phytec Mira
Add Phytec Mira device tree files, for use with pcm058.
>From Linux 5.6, commit 7111951b8d49 upstream

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Niel Fourie
3e21810743 dts-bindings: regulator: Add dlg,da9063-regulator
Add da9063-regulator bindings from Linux 5.6:
commit 7111951b8d49 upstream

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Peng Fan
86e9d7e814 imx8mm_evk: enlarge CONFIG_SYS_BOOTM_LEN
Enlarge CONFIG_SYS_BOOTM_LEN when booting FIT image with kernel.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:48 +08:00
Peng Fan
eb3967388e imx8m: implement armv8_el2_to_aarch32
Add iMX8M specific armv8_el2_to_aarch32 to let AArch64 mode U-Boot
could boot aarch32 mode linux with FIT image as below:

/dts-v1/;

/ {
        description = "Configuration to load ARM32 Linux";

        images {
                kernel@1 {
                        description = "ARM32 Linux kernel";
                        data = /incbin/("./Image");
                        type = "kernel";
                        arch = "arm";
                        os = "linux";
                        compression = "none";
                        load = <0x40008000>;
                        entry = <0x40008000>;
                        hash@1 {
                                algo = "md5";
                        };
                };
                fdt@1 {
                        description = "Flattened Device Tree blob";
                        data = /incbin/("./imx8mm-evk.dtb");
                        type = "flat_dt";
                        arch = "arm";
                        compression = "none";
                        load = <0x43000000>;
                        hash@1 {
                                algo = "md5";
                        };
                };
        };
        configurations {
                default = "config@1";

                config@1 {
                        description = "fsl-imx8mm-evk";
                        kernel = "kernel@1";
                        fdt = "fdt@1";
                };
        };
};

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:48 +08:00
Peng Fan
3c41728d80 imx8m: Refactor the OPTEE memory removal
Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.

When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:48 +08:00
Peng Fan
ec04ae4217 clk: imx8m: drop clk settings
We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
6036dba1c8 imx8m: disable nodes before kernel/mfgtool boot for fused part
To fused part, we need to disable nodes of dtb to let kernel boot.

To mfgtool, USB issue when using super-speed for mfgtool, temporally
work around the problem to use high-speed only.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
2707faf01f imx8mn/imx8mp: override env_get_offset and env_get_location
To use one defconfig for all boot device, we have to runtime set
env offset and return env medium according to the boot device.
This patch overrides the env_get_offset and env_get_location to
implement the feature.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
7a42bf0489 imx8m: power down fused cores
For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
d1eee7eed9 imx8mp: Add fused parts support
iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.

The configuration tables for enabled modules:
MIMX8ML8DVNLZAA          Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA          Quad Core, NPU, ISP
MIMX8ML6DVNLZAA          Quad Core, VPU, ISP
MIMX8ML5DVNLZAA          Quad Core, VPU
MIMX8ML4DVNLZAA          Quad Lite
MIMX8ML3DVNLZAA          Dual Core, VPU, NPU, ISP, DSP

Add the support in U-Boot

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
2f3c92060d imx8m: workaround ROM serror
ROM SError happens on two cases:

1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.

2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause
SError.

Since ROM mask SError until ATF unmask it, so then ATF always meets the
exception. This patch works around the issue in SPL by enabling SPL
Exception vectors table and the SError exception, take the exception
to eret immediately to clear the SError.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
3c9221ad27 imx8m: add eqos clk
Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the
weak function in driver

Add set_clk_eqos to configure eQoS clk

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
3c1c28d4e0 imx8m: add sdhc/nand/ecspi clk api
Current DM CLK is a bit complicated, for simplity, let DM clk only
support enable/disable/get_rate. For the expected rate settings,
we use non-DM clk to do that. Then we could have simple DM clk for
i.MX and could also share between SPL/U-Boot proper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
14254e646d imx8m: configure NoC clk
Configure NoC clk for better system performance

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
46a8a28bf6 imx8m: configure arm clk sources from PLL
A53 CCM root max support 1GHz, to support high freq, we need
to switch ARM clk sources from ARM PLL directly.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
ac9a451828 clk: imx8mp: Update imx8mp ccf clock driver
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
4b6548d17d clk: imx8mm/8mn: Add USB clocks
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
ee1f8b226f clk: clk-imx8mn: Update clock tree and support set parent
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
a65409420d clk: imx8mm: Add qspi clock
Add qspi clock

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
7ddb4ef3e1 clk: imx8mm: fix clk set parent
Fix clk set parent, so we could still have correct clocks after
parent changing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
d6498bc459 imx: remove imx sip file
We have switch to use arm_smccc_smc, no need to keep i.MX specific
sip wrapper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
4b8f22de16 imx: power-domain: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
c2eaa6eb09 imx8: fuse: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
bf26b9421e imx: bootaux: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
a2f143eaac imx8m: soc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
dc575201c8 imx8: misc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
683a91cdbd pinctrl: imx5: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
4b8c6030da pinctrl: imx8m: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
58db844fc8 pinctrl: imx7: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Oliver Chen
b335966958 drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Jian Li
3f63d27c17 imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set
this register to 1. This can avoid ddr bandwidth is lower
after booting with running for a while.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Jian Li
5865d14dde imx8mp: DDR performance tunning
1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Jian Li
dd2f41370d imx8mp: enable rd_port_urgent
Need to enable read urgent for NoC panic signal

Signed-off-by: Jian Li <jian.li@nxp.com
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Sherry Sun
f3acb02386 drivers: ddr: imx8mp: Add inline ECC feature support
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Jacky Bai
1eb325af16 driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m
The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.

Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Jacky Bai
355c620666 driver: ddr: imx: skip ddr_ss_gpr config on imx8mn
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Tom Rini
497c7598c4 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- Enable DM_SPI on siemens omap boards (Jagan)
- Dropped some non-dm supported omap3 boards (Jagan)
- Dropped non-dm code in omap3 spi driver (Jagan)
- Dropped non-dm code in kirkwood spi driver (Bhargav)
2020-07-11 17:40:00 -04:00